cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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digsy_mtc.dts (2803B)

      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * Digsy MTC board Device Tree Source
      4 *
      5 * Copyright (C) 2009 Semihalf
      6 *
      7 * Based on the CM5200 by M. Balakowicz
      8 */
      9
     10/include/ "mpc5200b.dtsi"
     11
     12&gpt0 { gpio-controller; fsl,has-wdt; };
     13&gpt1 { gpio-controller; };
     14
     15/ {
     16	model = "intercontrol,digsy-mtc";
     17	compatible = "intercontrol,digsy-mtc";
     18
     19	memory@0 {
     20		reg = <0x00000000 0x02000000>;	// 32MB
     21	};
     22
     23	soc5200@f0000000 {
     24		rtc@800 {
     25			status = "disabled";
     26		};
     27
     28		psc@2000 {		// PSC1
     29			status = "disabled";
     30		};
     31
     32		psc@2200 {		// PSC2
     33			status = "disabled";
     34		};
     35
     36		psc@2400 {		// PSC3
     37			status = "disabled";
     38		};
     39
     40		psc@2600 {		// PSC4
     41			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
     42		};
     43
     44		psc@2800 {		// PSC5
     45			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
     46		};
     47
     48		psc@2c00 {		// PSC6
     49			status = "disabled";
     50		};
     51
     52		ethernet@3000 {
     53			phy-handle = <&phy0>;
     54		};
     55
     56		mdio@3000 {
     57			phy0: ethernet-phy@0 {
     58				reg = <0>;
     59			};
     60		};
     61
     62		i2c@3d00 {
     63			eeprom@50 {
     64				compatible = "atmel,24c08";
     65				reg = <0x50>;
     66			};
     67
     68			rtc@56 {
     69				compatible = "microcrystal,rv3029";
     70				reg = <0x56>;
     71			};
     72
     73			rtc@68 {
     74				compatible = "dallas,ds1339";
     75				reg = <0x68>;
     76			};
     77		};
     78
     79		i2c@3d40 {
     80			status = "disabled";
     81		};
     82	};
     83
     84	pci@f0000d00 {
     85		interrupt-map-mask = <0xf800 0 0 7>;
     86		interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
     87				 0xc000 0 0 2 &mpc5200_pic 0 0 3
     88				 0xc000 0 0 3 &mpc5200_pic 0 0 3
     89				 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
     90		clock-frequency = <0>; // From boot loader
     91		interrupts = <2 8 0 2 9 0 2 10 0>;
     92		bus-range = <0 0>;
     93		ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000>,
     94			 <0x02000000 0 0x90000000 0x90000000 0 0x10000000>,
     95			 <0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
     96	};
     97
     98	localbus {
     99		ranges = <0 0 0xff000000 0x1000000
    100			  4 0 0x60000000 0x0001000>;
    101
    102		// 16-bit flash device at LocalPlus Bus CS0
    103		flash@0,0 {
    104			compatible = "cfi-flash";
    105			reg = <0 0 0x1000000>;
    106			bank-width = <2>;
    107			device-width = <2>;
    108			#size-cells = <1>;
    109			#address-cells = <1>;
    110
    111			partition@0 {
    112				label = "kernel";
    113				reg = <0x0 0x00200000>;
    114			};
    115			partition@200000 {
    116				label = "root";
    117				reg = <0x00200000 0x00300000>;
    118			};
    119			partition@500000 {
    120				label = "user";
    121				reg = <0x00500000 0x00a00000>;
    122			};
    123			partition@f00000 {
    124				label = "u-boot";
    125				reg = <0x00f00000 0x100000>;
    126			};
    127		};
    128
    129		can@4,0 {
    130			compatible = "nxp,sja1000";
    131			reg = <4 0x000 0x80>;
    132			nxp,external-clock-frequency = <24000000>;
    133			interrupts = <1 2 3>; // Level-low
    134		};
    135
    136		can@4,100 {
    137			compatible = "nxp,sja1000";
    138			reg = <4 0x100 0x80>;
    139			nxp,external-clock-frequency = <24000000>;
    140			interrupts = <1 2 3>;  // Level-low
    141		};
    142
    143		serial@4,200 {
    144			compatible = "nxp,sc28l92";
    145			reg = <4 0x200 0x10>;
    146			interrupts = <1 3 3>;
    147		};
    148	};
    149};