cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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e6500_power_isa.dtsi (2986B)


      1/*
      2 * e6500 Power ISA Device Tree Source (include)
      3 *
      4 * Copyright 2013 Freescale Semiconductor Inc.
      5 *
      6 * Redistribution and use in source and binary forms, with or without
      7 * modification, are permitted provided that the following conditions are met:
      8 *     * Redistributions of source code must retain the above copyright
      9 *       notice, this list of conditions and the following disclaimer.
     10 *     * Redistributions in binary form must reproduce the above copyright
     11 *       notice, this list of conditions and the following disclaimer in the
     12 *       documentation and/or other materials provided with the distribution.
     13 *     * Neither the name of Freescale Semiconductor nor the
     14 *       names of its contributors may be used to endorse or promote products
     15 *       derived from this software without specific prior written permission.
     16 *
     17 *
     18 * ALTERNATIVELY, this software may be distributed under the terms of the
     19 * GNU General Public License ("GPL") as published by the Free Software
     20 * Foundation, either version 2 of that License or (at your option) any
     21 * later version.
     22 *
     23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
     24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
     27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
     30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
     32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     33 */
     34
     35/ {
     36	cpus {
     37		power-isa-version = "2.06";
     38		power-isa-b;		// Base
     39		power-isa-e;		// Embedded
     40		power-isa-atb;		// Alternate Time Base
     41		power-isa-cs;		// Cache Specification
     42		power-isa-ds;		// Decorated Storage
     43		power-isa-e.ed;		// Embedded.Enhanced Debug
     44		power-isa-e.pd;		// Embedded.External PID
     45		power-isa-e.hv;		// Embedded.Hypervisor
     46		power-isa-e.le;		// Embedded.Little-Endian
     47		power-isa-e.pm;		// Embedded.Performance Monitor
     48		power-isa-e.pc;		// Embedded.Processor Control
     49		power-isa-ecl;		// Embedded Cache Locking
     50		power-isa-exp;		// External Proxy
     51		power-isa-fp;		// Floating Point
     52		power-isa-fp.r;		// Floating Point.Record
     53		power-isa-mmc;		// Memory Coherence
     54		power-isa-scpm;		// Store Conditional Page Mobility
     55		power-isa-wt;		// Wait
     56		power-isa-64;		// 64-bit
     57		power-isa-e.pt;		// Embedded.Page Table
     58		power-isa-e.hv.lrat;	// Embedded.Hypervisor.LRAT
     59		power-isa-e.em;		// Embedded Multi-Threading
     60		power-isa-v;		// Vector (AltiVec)
     61		fsl,eref-er;		// Enhanced Reservations (Load and Reserve and Store Cond.)
     62		fsl,eref-deo;		// Data Cache Extended Operations
     63		mmu-type = "power-embedded";
     64	};
     65};