kmcent2.dts (6303B)
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Keymile kmcent2 Device Tree Source, based on T1040RDB DTS 4 * 5 * (C) Copyright 2016 6 * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com 7 * 8 * Copyright 2014 - 2015 Freescale Semiconductor Inc. 9 */ 10 11/include/ "t104xsi-pre.dtsi" 12 13/ { 14 model = "keymile,kmcent2"; 15 compatible = "keymile,kmcent2"; 16 17 aliases { 18 front_phy = &front_phy; 19 }; 20 21 reserved-memory { 22 #address-cells = <2>; 23 #size-cells = <2>; 24 ranges; 25 26 bman_fbpr: bman-fbpr { 27 size = <0 0x1000000>; 28 alignment = <0 0x1000000>; 29 }; 30 qman_fqd: qman-fqd { 31 size = <0 0x400000>; 32 alignment = <0 0x400000>; 33 }; 34 qman_pfdr: qman-pfdr { 35 size = <0 0x2000000>; 36 alignment = <0 0x2000000>; 37 }; 38 }; 39 40 ifc: localbus@ffe124000 { 41 reg = <0xf 0xfe124000 0 0x2000>; 42 ranges = <0 0 0xf 0xe8000000 0x04000000 43 1 0 0xf 0xfa000000 0x00010000 44 2 0 0xf 0xfb000000 0x00010000 45 4 0 0xf 0xc0000000 0x08000000 46 6 0 0xf 0xd0000000 0x08000000 47 7 0 0xf 0xd8000000 0x08000000>; 48 49 nor@0,0 { 50 #address-cells = <1>; 51 #size-cells = <1>; 52 compatible = "cfi-flash"; 53 reg = <0x0 0x0 0x04000000>; 54 bank-width = <2>; 55 device-width = <2>; 56 }; 57 58 nand@1,0 { 59 #address-cells = <1>; 60 #size-cells = <1>; 61 compatible = "fsl,ifc-nand"; 62 reg = <0x1 0x0 0x10000>; 63 }; 64 65 board-control@2,0 { 66 compatible = "keymile,qriox"; 67 reg = <0x2 0x0 0x80>; 68 }; 69 70 chassis-mgmt@6,0 { 71 compatible = "keymile,bfticu"; 72 reg = <6 0 0x100>; 73 interrupt-controller; 74 interrupt-parent = <&mpic>; 75 interrupts = <11 1 0 0>; 76 #interrupt-cells = <1>; 77 }; 78 79 }; 80 81 memory { 82 device_type = "memory"; 83 }; 84 85 dcsr: dcsr@f00000000 { 86 ranges = <0x00000000 0xf 0x00000000 0x01072000>; 87 }; 88 89 bportals: bman-portals@ff4000000 { 90 ranges = <0x0 0xf 0xf4000000 0x2000000>; 91 }; 92 93 qportals: qman-portals@ff6000000 { 94 ranges = <0x0 0xf 0xf6000000 0x2000000>; 95 }; 96 97 soc: soc@ffe000000 { 98 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 99 reg = <0xf 0xfe000000 0 0x00001000>; 100 101 spi@110000 { 102 network-clock@1 { 103 compatible = "zarlink,zl30364"; 104 reg = <1>; 105 spi-max-frequency = <1000000>; 106 }; 107 }; 108 109 sdhc@114000 { 110 status = "disabled"; 111 }; 112 113 i2c@118000 { 114 clock-frequency = <100000>; 115 116 mux@70 { 117 compatible = "nxp,pca9547"; 118 reg = <0x70>; 119 #address-cells = <1>; 120 #size-cells = <0>; 121 i2c-mux-idle-disconnect; 122 123 i2c@0 { 124 reg = <0>; 125 #address-cells = <1>; 126 #size-cells = <0>; 127 128 eeprom@54 { 129 compatible = "atmel,24c02"; 130 reg = <0x54>; 131 pagesize = <2>; 132 read-only; 133 label = "ddr3-spd"; 134 }; 135 }; 136 137 i2c@7 { 138 reg = <7>; 139 #address-cells = <1>; 140 #size-cells = <0>; 141 142 temp-sensor@48 { 143 compatible = "national,lm75"; 144 reg = <0x48>; 145 label = "SENSOR_0"; 146 }; 147 temp-sensor@4a { 148 compatible = "national,lm75"; 149 reg = <0x4a>; 150 label = "SENSOR_2"; 151 }; 152 temp-sensor@4b { 153 compatible = "national,lm75"; 154 reg = <0x4b>; 155 label = "SENSOR_3"; 156 }; 157 }; 158 }; 159 }; 160 161 i2c@118100 { 162 clock-frequency = <100000>; 163 164 eeprom@50 { 165 compatible = "atmel,24c08"; 166 reg = <0x50>; 167 pagesize = <16>; 168 }; 169 170 eeprom@54 { 171 compatible = "atmel,24c08"; 172 reg = <0x54>; 173 pagesize = <16>; 174 }; 175 }; 176 177 i2c@119000 { 178 status = "disabled"; 179 }; 180 181 i2c@119100 { 182 status = "disabled"; 183 }; 184 185 serial2: serial@11d500 { 186 status = "disabled"; 187 }; 188 189 serial3: serial@11d600 { 190 status = "disabled"; 191 }; 192 193 usb0: usb@210000 { 194 status = "disabled"; 195 }; 196 usb1: usb@211000 { 197 status = "disabled"; 198 }; 199 200 display@180000 { 201 status = "disabled"; 202 }; 203 204 sata@220000 { 205 status = "disabled"; 206 }; 207 sata@221000 { 208 status = "disabled"; 209 }; 210 211 fman@400000 { 212 ethernet@e0000 { 213 phy-mode = "sgmii"; 214 fixed-link { 215 speed = <1000>; 216 full-duplex; 217 }; 218 }; 219 220 ethernet@e2000 { 221 phy-mode = "sgmii"; 222 fixed-link { 223 speed = <1000>; 224 full-duplex; 225 }; 226 }; 227 228 ethernet@e4000 { 229 status = "disabled"; 230 }; 231 232 ethernet@e6000 { 233 status = "disabled"; 234 }; 235 236 ethernet@e8000 { 237 phy-handle = <&front_phy>; 238 phy-mode = "rgmii-id"; 239 }; 240 241 mdio0: mdio@fc000 { 242 front_phy: ethernet-phy@11 { 243 reg = <0x11>; 244 }; 245 }; 246 }; 247 }; 248 249 250 pci0: pcie@ffe240000 { 251 reg = <0xf 0xfe240000 0 0x10000>; 252 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 253 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 254 pcie@0 { 255 ranges = <0x02000000 0 0xe0000000 256 0x02000000 0 0xe0000000 257 0 0x20000000 258 259 0x01000000 0 0x00000000 260 0x01000000 0 0x00000000 261 0 0x00010000>; 262 }; 263 }; 264 265 pci1: pcie@ffe250000 { 266 status = "disabled"; 267 reg = <0xf 0xfe250000 0 0x10000>; 268 ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000 269 0x01000000 0 0 0xf 0xf8010000 0 0x00010000>; 270 pcie@0 { 271 ranges = <0x02000000 0 0xe0000000 272 0x02000000 0 0xe0000000 273 0 0x10000000 274 275 0x01000000 0 0x00000000 276 0x01000000 0 0x00000000 277 0 0x00010000>; 278 }; 279 }; 280 281 pci2: pcie@ffe260000 { 282 status = "disabled"; 283 reg = <0xf 0xfe260000 0 0x10000>; 284 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000 285 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 286 pcie@0 { 287 ranges = <0x02000000 0 0xe0000000 288 0x02000000 0 0xe0000000 289 0 0x10000000 290 291 0x01000000 0 0x00000000 292 0x01000000 0 0x00000000 293 0 0x00010000>; 294 }; 295 }; 296 297 pci3: pcie@ffe270000 { 298 status = "disabled"; 299 reg = <0xf 0xfe270000 0 0x10000>; 300 ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000 301 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; 302 pcie@0 { 303 ranges = <0x02000000 0 0xe0000000 304 0x02000000 0 0xe0000000 305 0 0x10000000 306 307 0x01000000 0 0x00000000 308 0x01000000 0 0x00000000 309 0 0x00010000>; 310 }; 311 }; 312 313 qe: qe@ffe140000 { 314 ranges = <0x0 0xf 0xfe140000 0x40000>; 315 reg = <0xf 0xfe140000 0 0x480>; 316 brg-frequency = <0>; 317 bus-frequency = <0>; 318 319 si1: si@700 { 320 compatible = "fsl,t1040-qe-si"; 321 reg = <0x700 0x80>; 322 }; 323 324 siram1: siram@1000 { 325 compatible = "fsl,t1040-qe-siram"; 326 reg = <0x1000 0x800>; 327 }; 328 329 ucc_hdlc: ucc@2000 { 330 device_type = "hdlc"; 331 compatible = "fsl,ucc-hdlc"; 332 rx-clock-name = "clk9"; 333 tx-clock-name = "clk9"; 334 fsl,hdlc-bus; 335 }; 336 }; 337}; 338 339#include "t1040si-post.dtsi"