mpc8572ds_camp_core0.dts (1468B)
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * MPC8572 DS Core0 Device Tree Source in CAMP mode. 4 * 5 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache 6 * can be shared, all the other devices must be assigned to one core only. 7 * This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0, 8 * eth1, crypto, pci0, pci1. 9 * 10 * Copyright 2007-2009 Freescale Semiconductor Inc. 11 */ 12 13/include/ "mpc8572ds.dts" 14 15/ { 16 model = "fsl,MPC8572DS"; 17 compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP"; 18 19 cpus { 20 PowerPC,8572@0 { 21 }; 22 PowerPC,8572@1 { 23 status = "disabled"; 24 }; 25 }; 26 27 localbus@ffe05000 { 28 status = "disabled"; 29 }; 30 31 soc8572@ffe00000 { 32 serial@4600 { 33 status = "disabled"; 34 }; 35 dma@c300 { 36 status = "disabled"; 37 }; 38 gpio-controller@f000 { 39 }; 40 l2-cache-controller@20000 { 41 cache-size = <0x80000>; // L2, 512K 42 }; 43 ethernet@26000 { 44 status = "disabled"; 45 }; 46 mdio@26520 { 47 status = "disabled"; 48 }; 49 ethernet@27000 { 50 status = "disabled"; 51 }; 52 mdio@27520 { 53 status = "disabled"; 54 }; 55 pic@40000 { 56 protected-sources = < 57 31 32 33 37 38 39 /* enet2 enet3 */ 58 76 77 78 79 26 42 /* dma2 pci2 serial*/ 59 0xe4 0xe5 0xe6 0xe7 /* msi */ 60 >; 61 }; 62 63 msi@41600 { 64 msi-available-ranges = <0 0x80>; 65 interrupts = < 66 0xe0 0 0 0 67 0xe1 0 0 0 68 0xe2 0 0 0 69 0xe3 0 0 0>; 70 }; 71 timer@42100 { 72 status = "disabled"; 73 }; 74 }; 75 pcie@ffe0a000 { 76 status = "disabled"; 77 }; 78};