cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

p2020rdb-pc_32b.dts (3193B)

      1/*
      2 * P2020 RDB-PC 32Bit Physical Address Map Device Tree Source
      3 *
      4 * Copyright 2011 Freescale Semiconductor Inc.
      5 *
      6 * Redistribution and use in source and binary forms, with or without
      7 * modification, are permitted provided that the following conditions are met:
      8 *     * Redistributions of source code must retain the above copyright
      9 *       notice, this list of conditions and the following disclaimer.
     10 *     * Redistributions in binary form must reproduce the above copyright
     11 *       notice, this list of conditions and the following disclaimer in the
     12 *       documentation and/or other materials provided with the distribution.
     13 *     * Neither the name of Freescale Semiconductor nor the
     14 *       names of its contributors may be used to endorse or promote products
     15 *       derived from this software without specific prior written permission.
     16 *
     17 *
     18 * ALTERNATIVELY, this software may be distributed under the terms of the
     19 * GNU General Public License ("GPL") as published by the Free Software
     20 * Foundation, either version 2 of that License or (at your option) any
     21 * later version.
     22 *
     23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
     24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
     27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
     30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
     32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     33 */
     34
     35/include/ "p2020si-pre.dtsi"
     36
     37/ {
     38	model = "fsl,P2020RDB";
     39	compatible = "fsl,P2020RDB-PC";
     40
     41	memory {
     42		device_type = "memory";
     43	};
     44
     45	lbc: localbus@ffe05000 {
     46		reg = <0 0xffe05000 0 0x1000>;
     47
     48		/* NOR and NAND Flashes */
     49		ranges = <0x0 0x0 0x0 0xef000000 0x01000000
     50			  0x1 0x0 0x0 0xff800000 0x00040000
     51			  0x2 0x0 0x0 0xffb00000 0x00020000
     52			  0x3 0x0 0x0 0xffa00000 0x00020000>;
     53	};
     54
     55	soc: soc@ffe00000 {
     56		ranges = <0x0 0x0 0xffe00000 0x100000>;
     57	};
     58
     59	pci2: pcie@ffe08000 {
     60		reg = <0 0xffe08000 0 0x1000>;
     61		status = "disabled";
     62	};
     63
     64	pci1: pcie@ffe09000 {
     65		reg = <0 0xffe09000 0 0x1000>;
     66		ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
     67			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
     68		pcie@0 {
     69			ranges = <0x2000000 0x0 0xe0000000
     70				  0x2000000 0x0 0xe0000000
     71				  0x0 0x20000000
     72
     73				  0x1000000 0x0 0x0
     74				  0x1000000 0x0 0x0
     75				  0x0 0x100000>;
     76		};
     77	};
     78
     79	pci0: pcie@ffe0a000 {
     80		reg = <0 0xffe0a000 0 0x1000>;
     81		ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
     82			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
     83		pcie@0 {
     84			ranges = <0x2000000 0x0 0xe0000000
     85				  0x2000000 0x0 0xe0000000
     86				  0x0 0x20000000
     87
     88				  0x1000000 0x0 0x0
     89				  0x1000000 0x0 0x0
     90				  0x0 0x100000>;
     91		};
     92	};
     93};
     94
     95/include/ "p2020rdb-pc.dtsi"
     96/include/ "p2020si-post.dtsi"