qoriq-sec5.0-0.dtsi (3592B)
1/* 2 * QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ] 3 * 4 * Copyright 2012 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35crypto: crypto@300000 { 36 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 37 fsl,sec-era = <5>; 38 #address-cells = <1>; 39 #size-cells = <1>; 40 reg = <0x300000 0x10000>; 41 ranges = <0 0x300000 0x10000>; 42 interrupts = <92 2 0 0>; 43 44 sec_jr0: jr@1000 { 45 compatible = "fsl,sec-v5.0-job-ring", 46 "fsl,sec-v4.0-job-ring"; 47 reg = <0x1000 0x1000>; 48 interrupts = <88 2 0 0>; 49 }; 50 51 sec_jr1: jr@2000 { 52 compatible = "fsl,sec-v5.0-job-ring", 53 "fsl,sec-v4.0-job-ring"; 54 reg = <0x2000 0x1000>; 55 interrupts = <89 2 0 0>; 56 }; 57 58 sec_jr2: jr@3000 { 59 compatible = "fsl,sec-v5.0-job-ring", 60 "fsl,sec-v4.0-job-ring"; 61 reg = <0x3000 0x1000>; 62 interrupts = <90 2 0 0>; 63 }; 64 65 sec_jr3: jr@4000 { 66 compatible = "fsl,sec-v5.0-job-ring", 67 "fsl,sec-v4.0-job-ring"; 68 reg = <0x4000 0x1000>; 69 interrupts = <91 2 0 0>; 70 }; 71 72 rtic@6000 { 73 compatible = "fsl,sec-v5.0-rtic", 74 "fsl,sec-v4.0-rtic"; 75 #address-cells = <1>; 76 #size-cells = <1>; 77 reg = <0x6000 0x100>; 78 ranges = <0x0 0x6100 0xe00>; 79 80 rtic_a: rtic-a@0 { 81 compatible = "fsl,sec-v5.0-rtic-memory", 82 "fsl,sec-v4.0-rtic-memory"; 83 reg = <0x00 0x20 0x100 0x80>; 84 }; 85 86 rtic_b: rtic-b@20 { 87 compatible = "fsl,sec-v5.0-rtic-memory", 88 "fsl,sec-v4.0-rtic-memory"; 89 reg = <0x20 0x20 0x200 0x80>; 90 }; 91 92 rtic_c: rtic-c@40 { 93 compatible = "fsl,sec-v5.0-rtic-memory", 94 "fsl,sec-v4.0-rtic-memory"; 95 reg = <0x40 0x20 0x300 0x80>; 96 }; 97 98 rtic_d: rtic-d@60 { 99 compatible = "fsl,sec-v5.0-rtic-memory", 100 "fsl,sec-v4.0-rtic-memory"; 101 reg = <0x60 0x20 0x500 0x80>; 102 }; 103 }; 104}; 105 106sec_mon: sec_mon@314000 { 107 compatible = "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon"; 108 reg = <0x314000 0x1000>; 109 interrupts = <93 2 0 0>; 110};