cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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t1042d4rdb.dts (3018B)

      1/*
      2 * T1042D4RDB Device Tree Source
      3 *
      4 * Copyright 2015 Freescale Semiconductor Inc.
      5 *
      6 * Redistribution and use in source and binary forms, with or without
      7 * modification, are permitted provided that the following conditions are met:
      8 *     * Redistributions of source code must retain the above copyright
      9 *	 notice, this list of conditions and the following disclaimer.
     10 *     * Redistributions in binary form must reproduce the above copyright
     11 *	 notice, this list of conditions and the following disclaimer in the
     12 *	 documentation and/or other materials provided with the distribution.
     13 *     * Neither the name of Freescale Semiconductor nor the
     14 *	 names of its contributors may be used to endorse or promote products
     15 *	 derived from this software without specific prior written permission.
     16 *
     17 *
     18 * ALTERNATIVELY, this software may be distributed under the terms of the
     19 * GNU General Public License ("GPL") as published by the Free Software
     20 * Foundation, either version 2 of that License or (at your option) any
     21 * later version.
     22 *
     23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
     24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
     27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
     30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
     32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     33 */
     34
     35/include/ "t104xsi-pre.dtsi"
     36/include/ "t104xd4rdb.dtsi"
     37
     38/ {
     39	model = "fsl,T1042D4RDB";
     40	compatible = "fsl,T1042D4RDB";
     41	#address-cells = <2>;
     42	#size-cells = <2>;
     43	interrupt-parent = <&mpic>;
     44
     45	ifc: localbus@ffe124000 {
     46		cpld@3,0 {
     47			compatible = "fsl,t1040d4rdb-cpld",
     48					"fsl,deepsleep-cpld";
     49		};
     50	};
     51
     52	soc: soc@ffe000000 {
     53		fman0: fman@400000 {
     54			ethernet@e0000 {
     55				phy-handle = <&phy_sgmii_0>;
     56				phy-connection-type = "sgmii";
     57			};
     58
     59			ethernet@e2000 {
     60				phy-handle = <&phy_sgmii_1>;
     61				phy-connection-type = "sgmii";
     62			};
     63
     64			ethernet@e4000 {
     65				phy-handle = <&phy_sgmii_2>;
     66				phy-connection-type = "sgmii";
     67			};
     68
     69			ethernet@e6000 {
     70				phy-handle = <&phy_rgmii_0>;
     71				phy-connection-type = "rgmii";
     72			};
     73
     74			ethernet@e8000 {
     75				phy-handle = <&phy_rgmii_1>;
     76				phy-connection-type = "rgmii";
     77			};
     78
     79			mdio0: mdio@fc000 {
     80				phy_sgmii_0: ethernet-phy@2 {
     81					reg = <0x02>;
     82				};
     83
     84				phy_sgmii_1: ethernet-phy@3 {
     85					reg = <0x03>;
     86				};
     87
     88				phy_sgmii_2: ethernet-phy@1 {
     89					reg = <0x01>;
     90				};
     91
     92				phy_rgmii_0: ethernet-phy@4 {
     93					reg = <0x04>;
     94				};
     95
     96				phy_rgmii_1: ethernet-phy@5 {
     97					reg = <0x05>;
     98				};
     99			};
    100		};
    101	};
    102
    103};
    104
    105#include "t1042si-post.dtsi"