cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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t2080rdb.dts (3401B)

      1/*
      2 * T2080PCIe-RDB Board Device Tree Source
      3 *
      4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
      5 *
      6 * Redistribution and use in source and binary forms, with or without
      7 * modification, are permitted provided that the following conditions are met:
      8 *     * Redistributions of source code must retain the above copyright
      9 *	 notice, this list of conditions and the following disclaimer.
     10 *     * Redistributions in binary form must reproduce the above copyright
     11 *	 notice, this list of conditions and the following disclaimer in the
     12 *	 documentation and/or other materials provided with the distribution.
     13 *     * Neither the name of Freescale Semiconductor nor the
     14 *	 names of its contributors may be used to endorse or promote products
     15 *	 derived from this software without specific prior written permission.
     16 *
     17 *
     18 * ALTERNATIVELY, this software may be distributed under the terms of the
     19 * GNU General Public License ("GPL") as published by the Free Software
     20 * Foundation, either version 2 of that License or (at your option) any
     21 * later version.
     22 *
     23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
     24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
     27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
     30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
     32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     33 */
     34
     35/include/ "t208xsi-pre.dtsi"
     36/include/ "t208xrdb.dtsi"
     37
     38/ {
     39	model = "fsl,T2080RDB";
     40	compatible = "fsl,T2080RDB";
     41	#address-cells = <2>;
     42	#size-cells = <2>;
     43	interrupt-parent = <&mpic>;
     44
     45	rio: rapidio@ffe0c0000 {
     46		reg = <0xf 0xfe0c0000 0 0x11000>;
     47
     48		port1 {
     49			ranges = <0 0 0xc 0x20000000 0 0x10000000>;
     50		};
     51		port2 {
     52			ranges = <0 0 0xc 0x30000000 0 0x10000000>;
     53		};
     54	};
     55};
     56
     57&soc {
     58	fman@400000 {
     59		ethernet@e0000 {
     60			phy-handle = <&xg_aq1202_phy3>;
     61			phy-connection-type = "xgmii";
     62		};
     63
     64		ethernet@e2000 {
     65			phy-handle = <&xg_aq1202_phy4>;
     66			phy-connection-type = "xgmii";
     67		};
     68
     69		ethernet@e4000 {
     70			phy-handle = <&rgmii_phy1>;
     71			phy-connection-type = "rgmii";
     72		};
     73
     74		ethernet@e6000 {
     75			phy-handle = <&rgmii_phy2>;
     76			phy-connection-type = "rgmii";
     77		};
     78
     79		ethernet@f0000 {
     80			phy-handle = <&xg_cs4315_phy2>;
     81			phy-connection-type = "xgmii";
     82		};
     83
     84		ethernet@f2000 {
     85			phy-handle = <&xg_cs4315_phy1>;
     86			phy-connection-type = "xgmii";
     87		};
     88
     89		mdio@fc000 {
     90			rgmii_phy1: ethernet-phy@1 {
     91				reg = <0x1>;
     92			};
     93			rgmii_phy2: ethernet-phy@2 {
     94				reg = <0x2>;
     95			};
     96		};
     97
     98		mdio@fd000 {
     99			xg_cs4315_phy1: ethernet-phy@c {
    100				compatible = "ethernet-phy-id13e5.1002";
    101				reg = <0xc>;
    102			};
    103
    104			xg_cs4315_phy2: ethernet-phy@d {
    105				compatible = "ethernet-phy-id13e5.1002";
    106				reg = <0xd>;
    107			};
    108
    109			xg_aq1202_phy3: ethernet-phy@0 {
    110				compatible = "ethernet-phy-ieee802.3-c45";
    111				reg = <0x0>;
    112			};
    113
    114			xg_aq1202_phy4: ethernet-phy@1 {
    115				compatible = "ethernet-phy-ieee802.3-c45";
    116				reg = <0x1>;
    117			};
    118		};
    119	};
    120};
    121
    122/include/ "t2080si-post.dtsi"