cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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iss4xx.dts (2860B)

      1/*
      2 * Device Tree Source for IBM Embedded PPC 476 Platform
      3 *
      4 * Copyright 2010 Torez Smith, IBM Corporation.
      5 *
      6 * Based on earlier code:
      7 *    Copyright (c) 2006, 2007 IBM Corp.
      8 *    Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
      9 *
     10 * This file is licensed under the terms of the GNU General Public
     11 * License version 2.  This program is licensed "as is" without
     12 * any warranty of any kind, whether express or implied.
     13 */
     14
     15/dts-v1/;
     16
     17/ {
     18	#address-cells = <2>;
     19	#size-cells = <1>;
     20	model = "ibm,iss-4xx";
     21	compatible = "ibm,iss-4xx";
     22	dcr-parent = <&{/cpus/cpu@0}>;
     23
     24	aliases {
     25		serial0 = &UART0;
     26	};
     27
     28	cpus {
     29		#address-cells = <1>;
     30		#size-cells = <0>;
     31
     32		cpu@0 {
     33			device_type = "cpu";
     34			model = "PowerPC,4xx"; // real CPU changed in sim
     35			reg = <0x00000000>;
     36			clock-frequency = <100000000>; // 100Mhz :-)
     37			timebase-frequency = <100000000>;
     38			i-cache-line-size = <32>; // may need fixup in sim
     39			d-cache-line-size = <32>; // may need fixup in sim
     40			i-cache-size = <32768>; /* may need fixup in sim */
     41			d-cache-size = <32768>; /* may need fixup in sim */
     42			dcr-controller;
     43			dcr-access-method = "native";
     44		};
     45	};
     46
     47	memory {
     48		device_type = "memory";
     49		reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage
     50	};
     51
     52	UIC0: interrupt-controller0 {
     53		compatible = "ibm,uic-4xx", "ibm,uic";
     54		interrupt-controller;
     55		cell-index = <0>;
     56		dcr-reg = <0x0c0 0x009>;
     57		#address-cells = <0>;
     58		#size-cells = <0>;
     59		#interrupt-cells = <2>;
     60
     61	};
     62
     63	UIC1: interrupt-controller1 {
     64		compatible = "ibm,uic-4xx", "ibm,uic";
     65		interrupt-controller;
     66		cell-index = <1>;
     67		dcr-reg = <0x0d0 0x009>;
     68		#address-cells = <0>;
     69		#size-cells = <0>;
     70		#interrupt-cells = <2>;
     71		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
     72		interrupt-parent = <&UIC0>;
     73	};
     74
     75	plb {
     76		compatible = "ibm,plb-4xx", "ibm,plb4"; /* Could be PLB6, doesn't matter */
     77		#address-cells = <2>;
     78		#size-cells = <1>;
     79		ranges;
     80		clock-frequency = <0>; // Filled in by zImage
     81
     82		POB0: opb {
     83			compatible = "ibm,opb-4xx", "ibm,opb";
     84			#address-cells = <1>;
     85			#size-cells = <1>;
     86			/* Wish there was a nicer way of specifying a full 32-bit
     87			   range */
     88			ranges = <0x00000000 0x00000001 0x00000000 0x80000000
     89				  0x80000000 0x00000001 0x80000000 0x80000000>;
     90			clock-frequency = <0>; // Filled in by zImage
     91			UART0: serial@40000200 {
     92				device_type = "serial";
     93				compatible = "ns16550a";
     94				reg = <0x40000200 0x00000008>;
     95				virtual-reg = <0xe0000200>;
     96				clock-frequency = <11059200>;
     97				current-speed = <115200>;
     98				interrupt-parent = <&UIC0>;
     99				interrupts = <0x0 0x4>;
    100			};
    101		};
    102	};
    103
    104	nvrtc {
    105		compatible = "ds1743-nvram", "ds1743", "rtc-ds1743";
    106		reg = <0 0xEF703000 0x2000>;
    107	};
    108	iss-block {
    109		compatible = "ibm,iss-sim-block-device";
    110		reg = <0 0xEF701000 0x1000>;
    111	};
    112
    113	chosen {
    114		stdout-path = "/plb/opb/serial@40000200";
    115	};
    116};