cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mpc7448hpc2.dts (4287B)


      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * MPC7448HPC2 (Taiga) board Device Tree Source
      4 *
      5 * Copyright 2006, 2008 Freescale Semiconductor Inc.
      6 * 2006 Roy Zang <Roy Zang at freescale.com>.
      7 */
      8
      9/dts-v1/;
     10
     11/ {
     12	model = "mpc7448hpc2";
     13	compatible = "mpc74xx";
     14	#address-cells = <1>;
     15	#size-cells = <1>;
     16
     17	aliases {
     18		ethernet0 = &enet0;
     19		ethernet1 = &enet1;
     20
     21		serial0 = &serial0;
     22		serial1 = &serial1;
     23
     24		pci0 = &pci0;
     25	};
     26
     27	cpus {
     28		#address-cells = <1>;
     29		#size-cells =<0>;
     30				
     31		PowerPC,7448@0 {
     32			device_type = "cpu";
     33			reg = <0x0>;
     34			d-cache-line-size = <32>;	// 32 bytes
     35			i-cache-line-size = <32>;	// 32 bytes
     36			d-cache-size = <0x8000>;		// L1, 32K bytes
     37			i-cache-size = <0x8000>;		// L1, 32K bytes
     38			timebase-frequency = <0>;	// 33 MHz, from uboot
     39			clock-frequency = <0>;		// From U-Boot
     40			bus-frequency = <0>;		// From U-Boot
     41		};
     42	};
     43
     44	memory {
     45		device_type = "memory";
     46		reg = <0x0 0x20000000	// DDR2   512M at 0
     47		       >;
     48	};
     49
     50  	tsi108@c0000000 {
     51		#address-cells = <1>;
     52		#size-cells = <1>;
     53		device_type = "tsi-bridge";
     54		ranges = <0x0 0xc0000000 0x10000>;
     55		reg = <0xc0000000 0x10000>;
     56		bus-frequency = <0>;
     57
     58		i2c@7000 {
     59			interrupt-parent = <&mpic>;
     60			interrupts = <14 0>;
     61			reg = <0x7000 0x400>;
     62			device_type = "i2c";
     63			compatible  = "tsi108-i2c";
     64		};
     65
     66		MDIO: mdio@6000 {
     67			compatible = "tsi108-mdio";
     68			reg = <0x6000 0x50>;
     69			#address-cells = <1>;
     70			#size-cells = <0>;
     71
     72			phy8: ethernet-phy@8 {
     73				interrupt-parent = <&mpic>;
     74				interrupts = <2 1>;
     75				reg = <0x8>;
     76			};
     77
     78			phy9: ethernet-phy@9 {
     79				interrupt-parent = <&mpic>;
     80				interrupts = <2 1>;
     81				reg = <0x9>;
     82			};
     83
     84		};
     85
     86		enet0: ethernet@6200 {
     87			linux,network-index = <0>;
     88			#size-cells = <0>;
     89			device_type = "network";
     90			compatible = "tsi108-ethernet";
     91			reg = <0x6000 0x200>;
     92			address = [ 00 06 D2 00 00 01 ];
     93			interrupts = <16 2>;
     94			interrupt-parent = <&mpic>;
     95			mdio-handle = <&MDIO>;
     96			phy-handle = <&phy8>;
     97		};
     98
     99		enet1: ethernet@6600 {
    100			linux,network-index = <1>;
    101			#address-cells = <1>;
    102			#size-cells = <0>;
    103			device_type = "network";
    104			compatible = "tsi108-ethernet";
    105			reg = <0x6400 0x200>;
    106			address = [ 00 06 D2 00 00 02 ];
    107			interrupts = <17 2>;
    108			interrupt-parent = <&mpic>;
    109			mdio-handle = <&MDIO>;
    110			phy-handle = <&phy9>;
    111		};
    112
    113		serial0: serial@7808 {
    114			device_type = "serial";
    115			compatible = "ns16550";
    116			reg = <0x7808 0x200>;
    117			clock-frequency = <1064000000>;
    118			interrupts = <12 0>;
    119			interrupt-parent = <&mpic>;
    120		};
    121
    122		serial1: serial@7c08 {
    123			device_type = "serial";
    124			compatible = "ns16550";
    125			reg = <0x7c08 0x200>;
    126			clock-frequency = <1064000000>;
    127			interrupts = <13 0>;
    128			interrupt-parent = <&mpic>;
    129		};
    130
    131	  	mpic: pic@7400 {
    132			interrupt-controller;
    133			#address-cells = <0>;
    134			#interrupt-cells = <2>;
    135			reg = <0x7400 0x400>;
    136			compatible = "chrp,open-pic";
    137			device_type = "open-pic";
    138		};
    139		pci0: pci@1000 {
    140			compatible = "tsi108-pci";
    141			device_type = "pci";
    142			#interrupt-cells = <1>;
    143			#size-cells = <2>;
    144			#address-cells = <3>;
    145			reg = <0x1000 0x1000>;
    146			bus-range = <0 0>;
    147			ranges = <0x2000000 0x0 0xe0000000 0xe0000000 0x0 0x1a000000	
    148				  0x1000000 0x0 0x0 0xfa000000 0x0 0x10000>;
    149			clock-frequency = <133333332>;
    150			interrupt-parent = <&mpic>;
    151			interrupts = <23 2>;
    152			interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
    153			interrupt-map = <
    154
    155				/* IDSEL 0x11 */
    156				0x800 0x0 0x0 0x1 &RT0 0x24 0x0
    157				0x800 0x0 0x0 0x2 &RT0 0x25 0x0
    158				0x800 0x0 0x0 0x3 &RT0 0x26 0x0
    159				0x800 0x0 0x0 0x4 &RT0 0x27 0x0
    160
    161				/* IDSEL 0x12 */
    162				0x1000 0x0 0x0 0x1 &RT0 0x25 0x0
    163				0x1000 0x0 0x0 0x2 &RT0 0x26 0x0
    164				0x1000 0x0 0x0 0x3 &RT0 0x27 0x0
    165				0x1000 0x0 0x0 0x4 &RT0 0x24 0x0
    166
    167				/* IDSEL 0x13 */
    168				0x1800 0x0 0x0 0x1 &RT0 0x26 0x0
    169				0x1800 0x0 0x0 0x2 &RT0 0x27 0x0
    170				0x1800 0x0 0x0 0x3 &RT0 0x24 0x0
    171				0x1800 0x0 0x0 0x4 &RT0 0x25 0x0
    172
    173				/* IDSEL 0x14 */
    174				0x2000 0x0 0x0 0x1 &RT0 0x27 0x0
    175				0x2000 0x0 0x0 0x2 &RT0 0x24 0x0
    176				0x2000 0x0 0x0 0x3 &RT0 0x25 0x0
    177				0x2000 0x0 0x0 0x4 &RT0 0x26 0x0
    178				>;
    179
    180			RT0: router@1180 {
    181				clock-frequency = <0>;
    182				interrupt-controller;
    183				device_type = "pic-router";
    184				#address-cells = <0>;
    185				#interrupt-cells = <2>;
    186				big-endian;
    187				interrupts = <23 2>;
    188				interrupt-parent = <&mpic>;
    189			};
    190		};
    191	};
    192};