mpc8378_mds.dts (11170B)
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * MPC8378E MDS Device Tree Source 4 * 5 * Copyright 2007 Freescale Semiconductor Inc. 6 */ 7 8/dts-v1/; 9 10/ { 11 model = "fsl,mpc8378emds"; 12 compatible = "fsl,mpc8378emds","fsl,mpc837xmds"; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 aliases { 17 ethernet0 = &enet0; 18 ethernet1 = &enet1; 19 serial0 = &serial0; 20 serial1 = &serial1; 21 pci0 = &pci0; 22 pci1 = &pci1; 23 pci2 = &pci2; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 PowerPC,8378@0 { 31 device_type = "cpu"; 32 reg = <0x0>; 33 d-cache-line-size = <32>; 34 i-cache-line-size = <32>; 35 d-cache-size = <32768>; 36 i-cache-size = <32768>; 37 timebase-frequency = <0>; 38 bus-frequency = <0>; 39 clock-frequency = <0>; 40 }; 41 }; 42 43 memory { 44 device_type = "memory"; 45 reg = <0x00000000 0x20000000>; // 512MB at 0 46 }; 47 48 localbus@e0005000 { 49 #address-cells = <2>; 50 #size-cells = <1>; 51 compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus"; 52 reg = <0xe0005000 0x1000>; 53 interrupts = <77 0x8>; 54 interrupt-parent = <&ipic>; 55 56 // booting from NOR flash 57 ranges = <0 0x0 0xfe000000 0x02000000 58 1 0x0 0xf8000000 0x00008000 59 3 0x0 0xe0600000 0x00008000>; 60 61 flash@0,0 { 62 #address-cells = <1>; 63 #size-cells = <1>; 64 compatible = "cfi-flash"; 65 reg = <0 0x0 0x2000000>; 66 bank-width = <2>; 67 device-width = <1>; 68 69 u-boot@0 { 70 reg = <0x0 0x100000>; 71 read-only; 72 }; 73 74 fs@100000 { 75 reg = <0x100000 0x800000>; 76 }; 77 78 kernel@1d00000 { 79 reg = <0x1d00000 0x200000>; 80 }; 81 82 dtb@1f00000 { 83 reg = <0x1f00000 0x100000>; 84 }; 85 }; 86 87 bcsr@1,0 { 88 reg = <1 0x0 0x8000>; 89 compatible = "fsl,mpc837xmds-bcsr"; 90 }; 91 92 nand@3,0 { 93 #address-cells = <1>; 94 #size-cells = <1>; 95 compatible = "fsl,mpc8378-fcm-nand", 96 "fsl,elbc-fcm-nand"; 97 reg = <3 0x0 0x8000>; 98 99 u-boot@0 { 100 reg = <0x0 0x100000>; 101 read-only; 102 }; 103 104 kernel@100000 { 105 reg = <0x100000 0x300000>; 106 }; 107 108 fs@400000 { 109 reg = <0x400000 0x1c00000>; 110 }; 111 }; 112 }; 113 114 soc@e0000000 { 115 #address-cells = <1>; 116 #size-cells = <1>; 117 device_type = "soc"; 118 compatible = "simple-bus"; 119 ranges = <0x0 0xe0000000 0x00100000>; 120 reg = <0xe0000000 0x00000200>; 121 bus-frequency = <0>; 122 123 wdt@200 { 124 compatible = "mpc83xx_wdt"; 125 reg = <0x200 0x100>; 126 }; 127 128 sleep-nexus { 129 #address-cells = <1>; 130 #size-cells = <1>; 131 compatible = "simple-bus"; 132 sleep = <&pmc 0x0c000000>; 133 ranges; 134 135 i2c@3000 { 136 #address-cells = <1>; 137 #size-cells = <0>; 138 cell-index = <0>; 139 compatible = "fsl-i2c"; 140 reg = <0x3000 0x100>; 141 interrupts = <14 0x8>; 142 interrupt-parent = <&ipic>; 143 dfsrr; 144 145 rtc@68 { 146 compatible = "dallas,ds1374"; 147 reg = <0x68>; 148 interrupts = <19 0x8>; 149 interrupt-parent = <&ipic>; 150 }; 151 }; 152 153 sdhci@2e000 { 154 compatible = "fsl,mpc8378-esdhc", "fsl,esdhc"; 155 reg = <0x2e000 0x1000>; 156 interrupts = <42 0x8>; 157 interrupt-parent = <&ipic>; 158 sdhci,wp-inverted; 159 /* Filled in by U-Boot */ 160 clock-frequency = <0>; 161 }; 162 }; 163 164 i2c@3100 { 165 #address-cells = <1>; 166 #size-cells = <0>; 167 cell-index = <1>; 168 compatible = "fsl-i2c"; 169 reg = <0x3100 0x100>; 170 interrupts = <15 0x8>; 171 interrupt-parent = <&ipic>; 172 dfsrr; 173 }; 174 175 spi@7000 { 176 cell-index = <0>; 177 compatible = "fsl,spi"; 178 reg = <0x7000 0x1000>; 179 interrupts = <16 0x8>; 180 interrupt-parent = <&ipic>; 181 mode = "cpu"; 182 }; 183 184 dma@82a8 { 185 #address-cells = <1>; 186 #size-cells = <1>; 187 compatible = "fsl,mpc8378-dma", "fsl,elo-dma"; 188 reg = <0x82a8 4>; 189 ranges = <0 0x8100 0x1a8>; 190 interrupt-parent = <&ipic>; 191 interrupts = <71 8>; 192 cell-index = <0>; 193 dma-channel@0 { 194 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 195 reg = <0 0x80>; 196 cell-index = <0>; 197 interrupt-parent = <&ipic>; 198 interrupts = <71 8>; 199 }; 200 dma-channel@80 { 201 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 202 reg = <0x80 0x80>; 203 cell-index = <1>; 204 interrupt-parent = <&ipic>; 205 interrupts = <71 8>; 206 }; 207 dma-channel@100 { 208 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 209 reg = <0x100 0x80>; 210 cell-index = <2>; 211 interrupt-parent = <&ipic>; 212 interrupts = <71 8>; 213 }; 214 dma-channel@180 { 215 compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel"; 216 reg = <0x180 0x28>; 217 cell-index = <3>; 218 interrupt-parent = <&ipic>; 219 interrupts = <71 8>; 220 }; 221 }; 222 223 usb@23000 { 224 compatible = "fsl-usb2-dr"; 225 reg = <0x23000 0x1000>; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 interrupt-parent = <&ipic>; 229 interrupts = <38 0x8>; 230 dr_mode = "host"; 231 phy_type = "ulpi"; 232 sleep = <&pmc 0x00c00000>; 233 }; 234 235 enet0: ethernet@24000 { 236 #address-cells = <1>; 237 #size-cells = <1>; 238 cell-index = <0>; 239 device_type = "network"; 240 model = "eTSEC"; 241 compatible = "gianfar"; 242 reg = <0x24000 0x1000>; 243 ranges = <0x0 0x24000 0x1000>; 244 local-mac-address = [ 00 00 00 00 00 00 ]; 245 interrupts = <32 0x8 33 0x8 34 0x8>; 246 phy-connection-type = "mii"; 247 interrupt-parent = <&ipic>; 248 tbi-handle = <&tbi0>; 249 phy-handle = <&phy2>; 250 sleep = <&pmc 0xc0000000>; 251 fsl,magic-packet; 252 253 mdio@520 { 254 #address-cells = <1>; 255 #size-cells = <0>; 256 compatible = "fsl,gianfar-mdio"; 257 reg = <0x520 0x20>; 258 259 phy2: ethernet-phy@2 { 260 interrupt-parent = <&ipic>; 261 interrupts = <17 0x8>; 262 reg = <0x2>; 263 }; 264 265 phy3: ethernet-phy@3 { 266 interrupt-parent = <&ipic>; 267 interrupts = <18 0x8>; 268 reg = <0x3>; 269 }; 270 271 tbi0: tbi-phy@11 { 272 reg = <0x11>; 273 device_type = "tbi-phy"; 274 }; 275 }; 276 }; 277 278 enet1: ethernet@25000 { 279 #address-cells = <1>; 280 #size-cells = <1>; 281 cell-index = <1>; 282 device_type = "network"; 283 model = "eTSEC"; 284 compatible = "gianfar"; 285 reg = <0x25000 0x1000>; 286 ranges = <0x0 0x25000 0x1000>; 287 local-mac-address = [ 00 00 00 00 00 00 ]; 288 interrupts = <35 0x8 36 0x8 37 0x8>; 289 phy-connection-type = "mii"; 290 interrupt-parent = <&ipic>; 291 tbi-handle = <&tbi1>; 292 phy-handle = <&phy3>; 293 sleep = <&pmc 0x30000000>; 294 fsl,magic-packet; 295 296 mdio@520 { 297 #address-cells = <1>; 298 #size-cells = <0>; 299 compatible = "fsl,gianfar-tbi"; 300 reg = <0x520 0x20>; 301 302 tbi1: tbi-phy@11 { 303 reg = <0x11>; 304 device_type = "tbi-phy"; 305 }; 306 }; 307 }; 308 309 serial0: serial@4500 { 310 cell-index = <0>; 311 device_type = "serial"; 312 compatible = "fsl,ns16550", "ns16550"; 313 reg = <0x4500 0x100>; 314 clock-frequency = <0>; 315 interrupts = <9 0x8>; 316 interrupt-parent = <&ipic>; 317 }; 318 319 serial1: serial@4600 { 320 cell-index = <1>; 321 device_type = "serial"; 322 compatible = "fsl,ns16550", "ns16550"; 323 reg = <0x4600 0x100>; 324 clock-frequency = <0>; 325 interrupts = <10 0x8>; 326 interrupt-parent = <&ipic>; 327 }; 328 329 crypto@30000 { 330 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", 331 "fsl,sec2.1", "fsl,sec2.0"; 332 reg = <0x30000 0x10000>; 333 interrupts = <11 0x8>; 334 interrupt-parent = <&ipic>; 335 fsl,num-channels = <4>; 336 fsl,channel-fifo-len = <24>; 337 fsl,exec-units-mask = <0x9fe>; 338 fsl,descriptor-types-mask = <0x3ab0ebf>; 339 sleep = <&pmc 0x03000000>; 340 }; 341 342 /* IPIC 343 * interrupts cell = <intr #, sense> 344 * sense values match linux IORESOURCE_IRQ_* defines: 345 * sense == 8: Level, low assertion 346 * sense == 2: Edge, high-to-low change 347 */ 348 ipic: pic@700 { 349 compatible = "fsl,ipic"; 350 interrupt-controller; 351 #address-cells = <0>; 352 #interrupt-cells = <2>; 353 reg = <0x700 0x100>; 354 }; 355 356 pmc: power@b00 { 357 compatible = "fsl,mpc8378-pmc", "fsl,mpc8349-pmc"; 358 reg = <0xb00 0x100 0xa00 0x100>; 359 interrupts = <80 0x8>; 360 interrupt-parent = <&ipic>; 361 }; 362 }; 363 364 pci0: pci@e0008500 { 365 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 366 interrupt-map = < 367 368 /* IDSEL 0x11 */ 369 0x8800 0x0 0x0 0x1 &ipic 20 0x8 370 0x8800 0x0 0x0 0x2 &ipic 21 0x8 371 0x8800 0x0 0x0 0x3 &ipic 22 0x8 372 0x8800 0x0 0x0 0x4 &ipic 23 0x8 373 374 /* IDSEL 0x12 */ 375 0x9000 0x0 0x0 0x1 &ipic 22 0x8 376 0x9000 0x0 0x0 0x2 &ipic 23 0x8 377 0x9000 0x0 0x0 0x3 &ipic 20 0x8 378 0x9000 0x0 0x0 0x4 &ipic 21 0x8 379 380 /* IDSEL 0x13 */ 381 0x9800 0x0 0x0 0x1 &ipic 23 0x8 382 0x9800 0x0 0x0 0x2 &ipic 20 0x8 383 0x9800 0x0 0x0 0x3 &ipic 21 0x8 384 0x9800 0x0 0x0 0x4 &ipic 22 0x8 385 386 /* IDSEL 0x15 */ 387 0xa800 0x0 0x0 0x1 &ipic 20 0x8 388 0xa800 0x0 0x0 0x2 &ipic 21 0x8 389 0xa800 0x0 0x0 0x3 &ipic 22 0x8 390 0xa800 0x0 0x0 0x4 &ipic 23 0x8 391 392 /* IDSEL 0x16 */ 393 0xb000 0x0 0x0 0x1 &ipic 23 0x8 394 0xb000 0x0 0x0 0x2 &ipic 20 0x8 395 0xb000 0x0 0x0 0x3 &ipic 21 0x8 396 0xb000 0x0 0x0 0x4 &ipic 22 0x8 397 398 /* IDSEL 0x17 */ 399 0xb800 0x0 0x0 0x1 &ipic 22 0x8 400 0xb800 0x0 0x0 0x2 &ipic 23 0x8 401 0xb800 0x0 0x0 0x3 &ipic 20 0x8 402 0xb800 0x0 0x0 0x4 &ipic 21 0x8 403 404 /* IDSEL 0x18 */ 405 0xc000 0x0 0x0 0x1 &ipic 21 0x8 406 0xc000 0x0 0x0 0x2 &ipic 22 0x8 407 0xc000 0x0 0x0 0x3 &ipic 23 0x8 408 0xc000 0x0 0x0 0x4 &ipic 20 0x8>; 409 interrupt-parent = <&ipic>; 410 interrupts = <66 0x8>; 411 bus-range = <0x0 0x0>; 412 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 413 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 414 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>; 415 clock-frequency = <0>; 416 sleep = <&pmc 0x00010000>; 417 #interrupt-cells = <1>; 418 #size-cells = <2>; 419 #address-cells = <3>; 420 reg = <0xe0008500 0x100 /* internal registers */ 421 0xe0008300 0x8>; /* config space access registers */ 422 compatible = "fsl,mpc8349-pci"; 423 device_type = "pci"; 424 }; 425 426 pci1: pcie@e0009000 { 427 #address-cells = <3>; 428 #size-cells = <2>; 429 #interrupt-cells = <1>; 430 device_type = "pci"; 431 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie"; 432 reg = <0xe0009000 0x00001000>; 433 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000 434 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>; 435 bus-range = <0 255>; 436 interrupt-map-mask = <0xf800 0 0 7>; 437 interrupt-map = <0 0 0 1 &ipic 1 8 438 0 0 0 2 &ipic 1 8 439 0 0 0 3 &ipic 1 8 440 0 0 0 4 &ipic 1 8>; 441 sleep = <&pmc 0x00300000>; 442 clock-frequency = <0>; 443 444 pcie@0 { 445 #address-cells = <3>; 446 #size-cells = <2>; 447 device_type = "pci"; 448 reg = <0 0 0 0 0>; 449 ranges = <0x02000000 0 0xa8000000 450 0x02000000 0 0xa8000000 451 0 0x10000000 452 0x01000000 0 0x00000000 453 0x01000000 0 0x00000000 454 0 0x00800000>; 455 }; 456 }; 457 458 pci2: pcie@e000a000 { 459 #address-cells = <3>; 460 #size-cells = <2>; 461 #interrupt-cells = <1>; 462 device_type = "pci"; 463 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie"; 464 reg = <0xe000a000 0x00001000>; 465 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000 466 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>; 467 bus-range = <0 255>; 468 interrupt-map-mask = <0xf800 0 0 7>; 469 interrupt-map = <0 0 0 1 &ipic 2 8 470 0 0 0 2 &ipic 2 8 471 0 0 0 3 &ipic 2 8 472 0 0 0 4 &ipic 2 8>; 473 sleep = <&pmc 0x000c0000>; 474 clock-frequency = <0>; 475 476 pcie@0 { 477 #address-cells = <3>; 478 #size-cells = <2>; 479 device_type = "pci"; 480 reg = <0 0 0 0 0>; 481 ranges = <0x02000000 0 0xc8000000 482 0x02000000 0 0xc8000000 483 0 0x10000000 484 0x01000000 0 0x00000000 485 0x01000000 0 0x00000000 486 0 0x00800000>; 487 }; 488 }; 489};