cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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util.S (1682B)


      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2/*
      3 * Copied from <file:arch/powerpc/kernel/misc_32.S>
      4 *
      5 * This file contains miscellaneous low-level functions.
      6 *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
      7 *
      8 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
      9 * and Paul Mackerras.
     10 *
     11 * kexec bits:
     12 * Copyright (C) 2002-2003 Eric Biederman  <ebiederm@xmission.com>
     13 * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
     14 */
     15#include "ppc_asm.h"
     16
     17#define SPRN_PVR        0x11F   /* Processor Version Register */
     18
     19	.text
     20
     21/* udelay needs to know the period of the
     22 * timebase in nanoseconds.  This used to be hardcoded to be 60ns
     23 * (period of 66MHz/4).  Now a variable is used that is initialized to
     24 * 60 for backward compatibility, but it can be overridden as necessary
     25 * with code something like this:
     26 *    extern unsigned long timebase_period_ns;
     27 *    timebase_period_ns = 1000000000 / bd->bi_tbfreq;
     28 */
     29	.data
     30	.globl timebase_period_ns
     31timebase_period_ns:
     32	.long	60
     33
     34	.text
     35/*
     36 * Delay for a number of microseconds
     37 */
     38	.globl	udelay
     39udelay:
     40	mulli	r4,r3,1000	/* nanoseconds */
     41	/*  Change r4 to be the number of ticks using:
     42	 *	(nanoseconds + (timebase_period_ns - 1 )) / timebase_period_ns
     43	 *  timebase_period_ns defaults to 60 (16.6MHz) */
     44	mflr	r5
     45	bcl	20,31,0f
     460:	mflr	r6
     47	mtlr	r5
     48	addis	r5,r6,(timebase_period_ns-0b)@ha
     49	lwz	r5,(timebase_period_ns-0b)@l(r5)
     50	add	r4,r4,r5
     51	addi	r4,r4,-1
     52	divw	r4,r4,r5	/* BUS ticks */
     531:	MFTBU(r5)
     54	MFTBL(r6)
     55	MFTBU(r7)
     56	cmpw	0,r5,r7
     57	bne	1b		/* Get [synced] base time */
     58	addc	r9,r6,r4	/* Compute end time */
     59	addze	r8,r5
     602:	MFTBU(r5)
     61	cmpw	0,r5,r8
     62	blt	2b
     63	bgt	3f
     64	MFTBL(r6)
     65	cmpw	0,r6,r9
     66	blt	2b
     673:	blr