cputable.h (23552B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef __ASM_POWERPC_CPUTABLE_H 3#define __ASM_POWERPC_CPUTABLE_H 4 5 6#include <linux/types.h> 7#include <uapi/asm/cputable.h> 8#include <asm/asm-const.h> 9 10#ifndef __ASSEMBLY__ 11 12/* This structure can grow, it's real size is used by head.S code 13 * via the mkdefs mechanism. 14 */ 15struct cpu_spec; 16 17typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec); 18typedef void (*cpu_restore_t)(void); 19 20enum powerpc_pmc_type { 21 PPC_PMC_DEFAULT = 0, 22 PPC_PMC_IBM = 1, 23 PPC_PMC_PA6T = 2, 24 PPC_PMC_G4 = 3, 25}; 26 27struct pt_regs; 28 29extern int machine_check_generic(struct pt_regs *regs); 30extern int machine_check_4xx(struct pt_regs *regs); 31extern int machine_check_440A(struct pt_regs *regs); 32extern int machine_check_e500mc(struct pt_regs *regs); 33extern int machine_check_e500(struct pt_regs *regs); 34extern int machine_check_47x(struct pt_regs *regs); 35int machine_check_8xx(struct pt_regs *regs); 36int machine_check_83xx(struct pt_regs *regs); 37 38extern void cpu_down_flush_e500v2(void); 39extern void cpu_down_flush_e500mc(void); 40extern void cpu_down_flush_e5500(void); 41extern void cpu_down_flush_e6500(void); 42 43/* NOTE WELL: Update identify_cpu() if fields are added or removed! */ 44struct cpu_spec { 45 /* CPU is matched via (PVR & pvr_mask) == pvr_value */ 46 unsigned int pvr_mask; 47 unsigned int pvr_value; 48 49 char *cpu_name; 50 unsigned long cpu_features; /* Kernel features */ 51 unsigned int cpu_user_features; /* Userland features */ 52 unsigned int cpu_user_features2; /* Userland features v2 */ 53 unsigned int mmu_features; /* MMU features */ 54 55 /* cache line sizes */ 56 unsigned int icache_bsize; 57 unsigned int dcache_bsize; 58 59 /* flush caches inside the current cpu */ 60 void (*cpu_down_flush)(void); 61 62 /* number of performance monitor counters */ 63 unsigned int num_pmcs; 64 enum powerpc_pmc_type pmc_type; 65 66 /* this is called to initialize various CPU bits like L1 cache, 67 * BHT, SPD, etc... from head.S before branching to identify_machine 68 */ 69 cpu_setup_t cpu_setup; 70 /* Used to restore cpu setup on secondary processors and at resume */ 71 cpu_restore_t cpu_restore; 72 73 /* Used by oprofile userspace to select the right counters */ 74 char *oprofile_cpu_type; 75 76 /* Name of processor class, for the ELF AT_PLATFORM entry */ 77 char *platform; 78 79 /* Processor specific machine check handling. Return negative 80 * if the error is fatal, 1 if it was fully recovered and 0 to 81 * pass up (not CPU originated) */ 82 int (*machine_check)(struct pt_regs *regs); 83 84 /* 85 * Processor specific early machine check handler which is 86 * called in real mode to handle SLB and TLB errors. 87 */ 88 long (*machine_check_early)(struct pt_regs *regs); 89}; 90 91extern struct cpu_spec *cur_cpu_spec; 92 93extern unsigned int __start___ftr_fixup, __stop___ftr_fixup; 94 95extern void set_cur_cpu_spec(struct cpu_spec *s); 96extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr); 97extern void identify_cpu_name(unsigned int pvr); 98extern void do_feature_fixups(unsigned long value, void *fixup_start, 99 void *fixup_end); 100 101extern const char *powerpc_base_platform; 102 103#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS 104extern void cpu_feature_keys_init(void); 105#else 106static inline void cpu_feature_keys_init(void) { } 107#endif 108 109#endif /* __ASSEMBLY__ */ 110 111/* CPU kernel features */ 112 113/* Definitions for features that we have on both 32-bit and 64-bit chips */ 114#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001) 115#define CPU_FTR_ALTIVEC ASM_CONST(0x00000002) 116#define CPU_FTR_DBELL ASM_CONST(0x00000004) 117#define CPU_FTR_CAN_NAP ASM_CONST(0x00000008) 118#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00000010) 119// ASM_CONST(0x00000020) Free 120#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00000040) 121#define CPU_FTR_LWSYNC ASM_CONST(0x00000080) 122#define CPU_FTR_NOEXECUTE ASM_CONST(0x00000100) 123#define CPU_FTR_EMB_HV ASM_CONST(0x00000200) 124 125/* Definitions for features that only exist on 32-bit chips */ 126#ifdef CONFIG_PPC32 127#define CPU_FTR_L2CR ASM_CONST(0x00002000) 128#define CPU_FTR_SPEC7450 ASM_CONST(0x00004000) 129#define CPU_FTR_TAU ASM_CONST(0x00008000) 130#define CPU_FTR_CAN_DOZE ASM_CONST(0x00010000) 131#define CPU_FTR_L3CR ASM_CONST(0x00040000) 132#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00080000) 133#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00100000) 134#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00200000) 135#define CPU_FTR_NO_DPM ASM_CONST(0x00400000) 136#define CPU_FTR_476_DD2 ASM_CONST(0x00800000) 137#define CPU_FTR_NEED_COHERENT ASM_CONST(0x01000000) 138#define CPU_FTR_NO_BTIC ASM_CONST(0x02000000) 139#define CPU_FTR_PPC_LE ASM_CONST(0x04000000) 140#define CPU_FTR_SPE ASM_CONST(0x10000000) 141#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x20000000) 142#define CPU_FTR_INDEXED_DCR ASM_CONST(0x40000000) 143 144#else /* CONFIG_PPC32 */ 145/* Define these to 0 for the sake of tests in common code */ 146#define CPU_FTR_PPC_LE (0) 147#define CPU_FTR_SPE (0) 148#endif 149 150/* 151 * Definitions for the 64-bit processor unique features; 152 * on 32-bit, make the names available but defined to be 0. 153 */ 154#ifdef __powerpc64__ 155#define LONG_ASM_CONST(x) ASM_CONST(x) 156#else 157#define LONG_ASM_CONST(x) 0 158#endif 159 160#define CPU_FTR_REAL_LE LONG_ASM_CONST(0x0000000000001000) 161#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000000002000) 162#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000000008000) 163#define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000000010000) 164#define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000000000020000) 165#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000000000040000) 166#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000000000080000) 167#define CPU_FTR_SMT LONG_ASM_CONST(0x0000000000100000) 168#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000000000200000) 169#define CPU_FTR_PURR LONG_ASM_CONST(0x0000000000400000) 170#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000000000800000) 171#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000000001000000) 172#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000000002000000) 173#define CPU_FTR_VSX LONG_ASM_CONST(0x0000000004000000) 174#define CPU_FTR_SAO LONG_ASM_CONST(0x0000000008000000) 175#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000000010000000) 176#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0000000020000000) 177#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0000000040000000) 178#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0000000080000000) 179#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0000000100000000) 180#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0000000200000000) 181/* LONG_ASM_CONST(0x0000000400000000) Free */ 182#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0000000800000000) 183#define CPU_FTR_TM LONG_ASM_CONST(0x0000001000000000) 184#define CPU_FTR_CFAR LONG_ASM_CONST(0x0000002000000000) 185#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0000004000000000) 186#define CPU_FTR_DAWR LONG_ASM_CONST(0x0000008000000000) 187#define CPU_FTR_DABRX LONG_ASM_CONST(0x0000010000000000) 188#define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x0000020000000000) 189#define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x0000080000000000) 190#define CPU_FTR_P9_TM_HV_ASSIST LONG_ASM_CONST(0x0000100000000000) 191#define CPU_FTR_P9_TM_XER_SO_BUG LONG_ASM_CONST(0x0000200000000000) 192#define CPU_FTR_P9_TLBIE_STQ_BUG LONG_ASM_CONST(0x0000400000000000) 193#define CPU_FTR_P9_TIDR LONG_ASM_CONST(0x0000800000000000) 194#define CPU_FTR_P9_TLBIE_ERAT_BUG LONG_ASM_CONST(0x0001000000000000) 195#define CPU_FTR_P9_RADIX_PREFETCH_BUG LONG_ASM_CONST(0x0002000000000000) 196#define CPU_FTR_ARCH_31 LONG_ASM_CONST(0x0004000000000000) 197#define CPU_FTR_DAWR1 LONG_ASM_CONST(0x0008000000000000) 198 199#ifndef __ASSEMBLY__ 200 201#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE) 202 203/* We only set the altivec features if the kernel was compiled with altivec 204 * support 205 */ 206#ifdef CONFIG_ALTIVEC 207#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC 208#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC 209#else 210#define CPU_FTR_ALTIVEC_COMP 0 211#define PPC_FEATURE_HAS_ALTIVEC_COMP 0 212#endif 213 214/* We only set the VSX features if the kernel was compiled with VSX 215 * support 216 */ 217#ifdef CONFIG_VSX 218#define CPU_FTR_VSX_COMP CPU_FTR_VSX 219#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX 220#else 221#define CPU_FTR_VSX_COMP 0 222#define PPC_FEATURE_HAS_VSX_COMP 0 223#endif 224 225/* We only set the spe features if the kernel was compiled with spe 226 * support 227 */ 228#ifdef CONFIG_SPE 229#define CPU_FTR_SPE_COMP CPU_FTR_SPE 230#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE 231#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE 232#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE 233#else 234#define CPU_FTR_SPE_COMP 0 235#define PPC_FEATURE_HAS_SPE_COMP 0 236#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0 237#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0 238#endif 239 240/* We only set the TM feature if the kernel was compiled with TM supprt */ 241#ifdef CONFIG_PPC_TRANSACTIONAL_MEM 242#define CPU_FTR_TM_COMP CPU_FTR_TM 243#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM 244#define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC 245#else 246#define CPU_FTR_TM_COMP 0 247#define PPC_FEATURE2_HTM_COMP 0 248#define PPC_FEATURE2_HTM_NOSC_COMP 0 249#endif 250 251/* We need to mark all pages as being coherent if we're SMP or we have a 252 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II 253 * require it for PCI "streaming/prefetch" to work properly. 254 * This is also required by 52xx family. 255 */ 256#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ 257 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \ 258 || defined(CONFIG_PPC_MPC52xx) 259#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT 260#else 261#define CPU_FTR_COMMON 0 262#endif 263 264/* The powersave features NAP & DOZE seems to confuse BDI when 265 debugging. So if a BDI is used, disable theses 266 */ 267#ifndef CONFIG_BDI_SWITCH 268#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE 269#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP 270#else 271#define CPU_FTR_MAYBE_CAN_DOZE 0 272#define CPU_FTR_MAYBE_CAN_NAP 0 273#endif 274 275#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ 276 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE | CPU_FTR_NOEXECUTE) 277#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_PPC_LE) 278#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \ 279 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ 280 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 281#define CPU_FTRS_740 (CPU_FTR_COMMON | \ 282 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ 283 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ 284 CPU_FTR_PPC_LE) 285#define CPU_FTRS_750 (CPU_FTR_COMMON | \ 286 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ 287 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ 288 CPU_FTR_PPC_LE) 289#define CPU_FTRS_750CL (CPU_FTRS_750) 290#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM) 291#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM) 292#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX) 293#define CPU_FTRS_750GX (CPU_FTRS_750FX) 294#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \ 295 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ 296 CPU_FTR_ALTIVEC_COMP | \ 297 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 298#define CPU_FTRS_7400 (CPU_FTR_COMMON | \ 299 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ 300 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \ 301 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 302#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \ 303 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 304 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 305 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 306#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \ 307 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 308 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 309 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 310 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 311#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \ 312 CPU_FTR_NEED_PAIRED_STWCX | \ 313 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 314 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 315 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 316#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \ 317 CPU_FTR_NEED_PAIRED_STWCX | \ 318 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ 319 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 320#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \ 321 CPU_FTR_NEED_PAIRED_STWCX | \ 322 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 323 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 324 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 325 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 326#define CPU_FTRS_7455 (CPU_FTR_COMMON | \ 327 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 328 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 329 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 330#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \ 331 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 332 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 333 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \ 334 CPU_FTR_NEED_PAIRED_STWCX) 335#define CPU_FTRS_7447 (CPU_FTR_COMMON | \ 336 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 337 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 338 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 339#define CPU_FTRS_7447A (CPU_FTR_COMMON | \ 340 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 341 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 342 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 343#define CPU_FTRS_7448 (CPU_FTR_COMMON | \ 344 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 345 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 346 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 347#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_NOEXECUTE) 348#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ 349 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NOEXECUTE) 350#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \ 351 CPU_FTR_MAYBE_CAN_NAP | \ 352 CPU_FTR_COMMON | CPU_FTR_NOEXECUTE) 353#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \ 354 CPU_FTR_MAYBE_CAN_NAP | \ 355 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE | CPU_FTR_NOEXECUTE) 356#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON) 357#define CPU_FTRS_8XX (CPU_FTR_NOEXECUTE) 358#define CPU_FTRS_40X (CPU_FTR_NOEXECUTE) 359#define CPU_FTRS_44X (CPU_FTR_NOEXECUTE) 360#define CPU_FTRS_440x6 (CPU_FTR_NOEXECUTE | \ 361 CPU_FTR_INDEXED_DCR) 362#define CPU_FTRS_47X (CPU_FTRS_440x6) 363#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | \ 364 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \ 365 CPU_FTR_NOEXECUTE) 366#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | \ 367 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \ 368 CPU_FTR_NOEXECUTE) 369#define CPU_FTRS_E500MC ( \ 370 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 371 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV) 372/* 373 * e5500/e6500 erratum A-006958 is a timebase bug that can use the 374 * same workaround as CPU_FTR_CELL_TB_BUG. 375 */ 376#define CPU_FTRS_E5500 ( \ 377 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 378 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 379 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG) 380#define CPU_FTRS_E6500 ( \ 381 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 382 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 383 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \ 384 CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT) 385 386/* 64-bit CPUs */ 387#define CPU_FTRS_PPC970 (CPU_FTR_LWSYNC | \ 388 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 389 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \ 390 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \ 391 CPU_FTR_HVMODE | CPU_FTR_DABRX) 392#define CPU_FTRS_POWER5 (CPU_FTR_LWSYNC | \ 393 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 394 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 395 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \ 396 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX) 397#define CPU_FTRS_POWER6 (CPU_FTR_LWSYNC | \ 398 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 399 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 400 CPU_FTR_COHERENT_ICACHE | \ 401 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 402 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \ 403 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \ 404 CPU_FTR_DABRX) 405#define CPU_FTRS_POWER7 (CPU_FTR_LWSYNC | \ 406 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 407 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 408 CPU_FTR_COHERENT_ICACHE | \ 409 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 410 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ 411 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 412 CPU_FTR_CFAR | CPU_FTR_HVMODE | \ 413 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX ) 414#define CPU_FTRS_POWER8 (CPU_FTR_LWSYNC | \ 415 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 416 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 417 CPU_FTR_COHERENT_ICACHE | \ 418 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 419 CPU_FTR_DSCR | CPU_FTR_SAO | \ 420 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 421 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ 422 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \ 423 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP ) 424#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG) 425#define CPU_FTRS_POWER9 (CPU_FTR_LWSYNC | \ 426 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 427 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 428 CPU_FTR_COHERENT_ICACHE | \ 429 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 430 CPU_FTR_DSCR | CPU_FTR_SAO | \ 431 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 432 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ 433 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \ 434 CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_P9_TLBIE_STQ_BUG | \ 435 CPU_FTR_P9_TLBIE_ERAT_BUG | CPU_FTR_P9_TIDR) 436#define CPU_FTRS_POWER9_DD2_0 (CPU_FTRS_POWER9 | CPU_FTR_P9_RADIX_PREFETCH_BUG) 437#define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | \ 438 CPU_FTR_P9_RADIX_PREFETCH_BUG | \ 439 CPU_FTR_POWER9_DD2_1) 440#define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \ 441 CPU_FTR_P9_TM_HV_ASSIST | \ 442 CPU_FTR_P9_TM_XER_SO_BUG) 443#define CPU_FTRS_POWER9_DD2_3 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \ 444 CPU_FTR_P9_TM_HV_ASSIST | \ 445 CPU_FTR_P9_TM_XER_SO_BUG | \ 446 CPU_FTR_DAWR) 447#define CPU_FTRS_POWER10 (CPU_FTR_LWSYNC | \ 448 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 449 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 450 CPU_FTR_COHERENT_ICACHE | \ 451 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 452 CPU_FTR_DSCR | CPU_FTR_SAO | \ 453 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 454 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ 455 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \ 456 CPU_FTR_ARCH_300 | CPU_FTR_ARCH_31 | \ 457 CPU_FTR_DAWR | CPU_FTR_DAWR1) 458#define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \ 459 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 460 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 461 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \ 462 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX) 463#define CPU_FTRS_PA6T (CPU_FTR_LWSYNC | \ 464 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \ 465 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX) 466#define CPU_FTRS_COMPATIBLE (CPU_FTR_PPCAS_ARCH_V2) 467 468#ifdef CONFIG_PPC64 469#ifdef CONFIG_PPC_BOOK3E 470#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500) 471#else 472#ifdef CONFIG_CPU_LITTLE_ENDIAN 473#define CPU_FTRS_POSSIBLE \ 474 (CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \ 475 CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \ 476 CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | \ 477 CPU_FTRS_POWER9_DD2_3 | CPU_FTRS_POWER10) 478#else 479#define CPU_FTRS_POSSIBLE \ 480 (CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \ 481 CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \ 482 CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \ 483 CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \ 484 CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | \ 485 CPU_FTRS_POWER9_DD2_3 | CPU_FTRS_POWER10) 486#endif /* CONFIG_CPU_LITTLE_ENDIAN */ 487#endif 488#else 489enum { 490 CPU_FTRS_POSSIBLE = 491#ifdef CONFIG_PPC_BOOK3S_604 492 CPU_FTRS_604 | CPU_FTRS_740_NOTAU | 493 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 | 494 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX | 495 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 | 496 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 | 497 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 | 498 CPU_FTRS_7447 | CPU_FTRS_7447A | 499 CPU_FTRS_CLASSIC32 | 500#endif 501#ifdef CONFIG_PPC_BOOK3S_603 502 CPU_FTRS_603 | CPU_FTRS_82XX | 503 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 | 504#endif 505#ifdef CONFIG_PPC_8xx 506 CPU_FTRS_8XX | 507#endif 508#ifdef CONFIG_40x 509 CPU_FTRS_40X | 510#endif 511#ifdef CONFIG_PPC_47x 512 CPU_FTRS_47X | CPU_FTR_476_DD2 | 513#elif defined(CONFIG_44x) 514 CPU_FTRS_44X | CPU_FTRS_440x6 | 515#endif 516#ifdef CONFIG_E500 517 CPU_FTRS_E500 | CPU_FTRS_E500_2 | 518#endif 519#ifdef CONFIG_PPC_E500MC 520 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 | 521#endif 522 0, 523}; 524#endif /* __powerpc64__ */ 525 526#ifdef CONFIG_PPC64 527#ifdef CONFIG_PPC_BOOK3E 528#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500) 529#else 530 531#ifdef CONFIG_PPC_DT_CPU_FTRS 532#define CPU_FTRS_DT_CPU_BASE \ 533 (CPU_FTR_LWSYNC | \ 534 CPU_FTR_FPU_UNAVAILABLE | \ 535 CPU_FTR_NOEXECUTE | \ 536 CPU_FTR_COHERENT_ICACHE | \ 537 CPU_FTR_STCX_CHECKS_ADDRESS | \ 538 CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 539 CPU_FTR_DAWR | \ 540 CPU_FTR_ARCH_206 | \ 541 CPU_FTR_ARCH_207S) 542#else 543#define CPU_FTRS_DT_CPU_BASE (~0ul) 544#endif 545 546#ifdef CONFIG_CPU_LITTLE_ENDIAN 547#define CPU_FTRS_ALWAYS \ 548 (CPU_FTRS_POSSIBLE & ~CPU_FTR_HVMODE & CPU_FTRS_POWER7 & \ 549 CPU_FTRS_POWER8E & CPU_FTRS_POWER8 & CPU_FTRS_POWER9 & \ 550 CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_POWER9_DD2_2 & \ 551 CPU_FTRS_POWER10 & CPU_FTRS_DT_CPU_BASE) 552#else 553#define CPU_FTRS_ALWAYS \ 554 (CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \ 555 CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \ 556 CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \ 557 ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & CPU_FTRS_POWER9 & \ 558 CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_POWER9_DD2_2 & \ 559 CPU_FTRS_POWER10 & CPU_FTRS_DT_CPU_BASE) 560#endif /* CONFIG_CPU_LITTLE_ENDIAN */ 561#endif 562#else 563enum { 564 CPU_FTRS_ALWAYS = 565#ifdef CONFIG_PPC_BOOK3S_604 566 CPU_FTRS_604 & CPU_FTRS_740_NOTAU & 567 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 & 568 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX & 569 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 & 570 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 & 571 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 & 572 CPU_FTRS_7447 & CPU_FTRS_7447A & 573 CPU_FTRS_CLASSIC32 & 574#endif 575#ifdef CONFIG_PPC_BOOK3S_603 576 CPU_FTRS_603 & CPU_FTRS_82XX & 577 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 & 578#endif 579#ifdef CONFIG_PPC_8xx 580 CPU_FTRS_8XX & 581#endif 582#ifdef CONFIG_40x 583 CPU_FTRS_40X & 584#endif 585#ifdef CONFIG_PPC_47x 586 CPU_FTRS_47X & 587#elif defined(CONFIG_44x) 588 CPU_FTRS_44X & CPU_FTRS_440x6 & 589#endif 590#ifdef CONFIG_E500 591 CPU_FTRS_E500 & CPU_FTRS_E500_2 & 592#endif 593#ifdef CONFIG_PPC_E500MC 594 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 & 595#endif 596 ~CPU_FTR_EMB_HV & /* can be removed at runtime */ 597 CPU_FTRS_POSSIBLE, 598}; 599#endif /* __powerpc64__ */ 600 601/* 602 * Maximum number of hw breakpoint supported on powerpc. Number of 603 * breakpoints supported by actual hw might be less than this, which 604 * is decided at run time in nr_wp_slots(). 605 */ 606#define HBP_NUM_MAX 2 607 608#endif /* !__ASSEMBLY__ */ 609 610#endif /* __ASM_POWERPC_CPUTABLE_H */