cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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probes.h (2517B)

      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2#ifndef _ASM_POWERPC_PROBES_H
      3#define _ASM_POWERPC_PROBES_H
      4#ifdef __KERNEL__
      5/*
      6 * Definitions common to probes files
      7 *
      8 * Copyright IBM Corporation, 2012
      9 */
     10#include <linux/types.h>
     11#include <asm/disassemble.h>
     12
     13typedef u32 ppc_opcode_t;
     14#define BREAKPOINT_INSTRUCTION	0x7fe00008	/* trap */
     15
     16/* Trap definitions per ISA */
     17#define IS_TW(instr)		(((instr) & 0xfc0007fe) == 0x7c000008)
     18#define IS_TD(instr)		(((instr) & 0xfc0007fe) == 0x7c000088)
     19#define IS_TDI(instr)		(((instr) & 0xfc000000) == 0x08000000)
     20#define IS_TWI(instr)		(((instr) & 0xfc000000) == 0x0c000000)
     21
     22#ifdef CONFIG_PPC64
     23#define is_trap(instr)		(IS_TW(instr) || IS_TD(instr) || \
     24				IS_TWI(instr) || IS_TDI(instr))
     25#else
     26#define is_trap(instr)		(IS_TW(instr) || IS_TWI(instr))
     27#endif /* CONFIG_PPC64 */
     28
     29#ifdef CONFIG_PPC_ADV_DEBUG_REGS
     30#define MSR_SINGLESTEP	(MSR_DE)
     31#else
     32#define MSR_SINGLESTEP	(MSR_SE)
     33#endif
     34
     35static inline bool can_single_step(u32 inst)
     36{
     37	switch (get_op(inst)) {
     38	case OP_TRAP_64:	return false;
     39	case OP_TRAP:		return false;
     40	case OP_SC:		return false;
     41	case OP_19:
     42		switch (get_xop(inst)) {
     43		case OP_19_XOP_RFID:		return false;
     44		case OP_19_XOP_RFMCI:		return false;
     45		case OP_19_XOP_RFDI:		return false;
     46		case OP_19_XOP_RFI:		return false;
     47		case OP_19_XOP_RFCI:		return false;
     48		case OP_19_XOP_RFSCV:		return false;
     49		case OP_19_XOP_HRFID:		return false;
     50		case OP_19_XOP_URFID:		return false;
     51		case OP_19_XOP_STOP:		return false;
     52		case OP_19_XOP_DOZE:		return false;
     53		case OP_19_XOP_NAP:		return false;
     54		case OP_19_XOP_SLEEP:		return false;
     55		case OP_19_XOP_RVWINKLE:	return false;
     56		}
     57		break;
     58	case OP_31:
     59		switch (get_xop(inst)) {
     60		case OP_31_XOP_TRAP:		return false;
     61		case OP_31_XOP_TRAP_64:		return false;
     62		case OP_31_XOP_MTMSR:		return false;
     63		case OP_31_XOP_MTMSRD:		return false;
     64		}
     65		break;
     66	}
     67	return true;
     68}
     69
     70/* Enable single stepping for the current task */
     71static inline void enable_single_step(struct pt_regs *regs)
     72{
     73	regs_set_return_msr(regs, regs->msr | MSR_SINGLESTEP);
     74#ifdef CONFIG_PPC_ADV_DEBUG_REGS
     75	/*
     76	 * We turn off Critical Input Exception(CE) to ensure that the single
     77	 * step will be for the instruction we have the probe on; if we don't,
     78	 * it is possible we'd get the single step reported for CE.
     79	 */
     80	regs_set_return_msr(regs, regs->msr & ~MSR_CE);
     81	mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | DBCR0_IC | DBCR0_IDM);
     82#ifdef CONFIG_PPC_47x
     83	isync();
     84#endif
     85#endif
     86}
     87
     88
     89#endif /* __KERNEL__ */
     90#endif	/* _ASM_POWERPC_PROBES_H */