cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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xor.h (1017B)

      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2/*
      3 *
      4 * Copyright (C) IBM Corporation, 2012
      5 *
      6 * Author: Anton Blanchard <anton@au.ibm.com>
      7 */
      8#ifndef _ASM_POWERPC_XOR_H
      9#define _ASM_POWERPC_XOR_H
     10
     11#ifdef CONFIG_ALTIVEC
     12
     13#include <asm/cputable.h>
     14#include <asm/cpu_has_feature.h>
     15#include <asm/xor_altivec.h>
     16
     17static struct xor_block_template xor_block_altivec = {
     18	.name = "altivec",
     19	.do_2 = xor_altivec_2,
     20	.do_3 = xor_altivec_3,
     21	.do_4 = xor_altivec_4,
     22	.do_5 = xor_altivec_5,
     23};
     24
     25#define XOR_SPEED_ALTIVEC()				\
     26	do {						\
     27		if (cpu_has_feature(CPU_FTR_ALTIVEC))	\
     28			xor_speed(&xor_block_altivec);	\
     29	} while (0)
     30#else
     31#define XOR_SPEED_ALTIVEC()
     32#endif
     33
     34/* Also try the generic routines. */
     35#include <asm-generic/xor.h>
     36
     37#undef XOR_TRY_TEMPLATES
     38#define XOR_TRY_TEMPLATES				\
     39do {							\
     40	xor_speed(&xor_block_8regs);			\
     41	xor_speed(&xor_block_8regs_p);			\
     42	xor_speed(&xor_block_32regs);			\
     43	xor_speed(&xor_block_32regs_p);			\
     44	XOR_SPEED_ALTIVEC();				\
     45} while (0)
     46
     47#endif /* _ASM_POWERPC_XOR_H */