cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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eeh.h (2233B)


      1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
      2/*
      3 * This program is free software; you can redistribute it and/or modify
      4 * it under the terms of the GNU General Public License, version 2, as
      5 * published by the Free Software Foundation.
      6 *
      7 * This program is distributed in the hope that it will be useful,
      8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
      9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     10 * GNU General Public License for more details.
     11 *
     12 * You should have received a copy of the GNU General Public License
     13 * along with this program; if not, write to the Free Software
     14 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
     15 *
     16 * Copyright IBM Corp. 2015
     17 *
     18 * Authors: Gavin Shan <gwshan@linux.vnet.ibm.com>
     19 */
     20
     21#ifndef _ASM_POWERPC_EEH_H
     22#define _ASM_POWERPC_EEH_H
     23
     24/* PE states */
     25#define EEH_PE_STATE_NORMAL		0	/* Normal state		*/
     26#define EEH_PE_STATE_RESET		1	/* PE reset asserted	*/
     27#define EEH_PE_STATE_STOPPED_IO_DMA	2	/* Frozen PE		*/
     28#define EEH_PE_STATE_STOPPED_DMA	4	/* Stopped DMA only	*/
     29#define EEH_PE_STATE_UNAVAIL		5	/* Unavailable		*/
     30
     31/* EEH error types and functions */
     32#define EEH_ERR_TYPE_32			0       /* 32-bits error	*/
     33#define EEH_ERR_TYPE_64			1       /* 64-bits error	*/
     34#define EEH_ERR_FUNC_MIN		0
     35#define EEH_ERR_FUNC_LD_MEM_ADDR	0	/* Memory load	*/
     36#define EEH_ERR_FUNC_LD_MEM_DATA	1
     37#define EEH_ERR_FUNC_LD_IO_ADDR		2	/* IO load	*/
     38#define EEH_ERR_FUNC_LD_IO_DATA		3
     39#define EEH_ERR_FUNC_LD_CFG_ADDR	4	/* Config load	*/
     40#define EEH_ERR_FUNC_LD_CFG_DATA	5
     41#define EEH_ERR_FUNC_ST_MEM_ADDR	6	/* Memory store	*/
     42#define EEH_ERR_FUNC_ST_MEM_DATA	7
     43#define EEH_ERR_FUNC_ST_IO_ADDR		8	/* IO store	*/
     44#define EEH_ERR_FUNC_ST_IO_DATA		9
     45#define EEH_ERR_FUNC_ST_CFG_ADDR	10	/* Config store	*/
     46#define EEH_ERR_FUNC_ST_CFG_DATA	11
     47#define EEH_ERR_FUNC_DMA_RD_ADDR	12	/* DMA read	*/
     48#define EEH_ERR_FUNC_DMA_RD_DATA	13
     49#define EEH_ERR_FUNC_DMA_RD_MASTER	14
     50#define EEH_ERR_FUNC_DMA_RD_TARGET	15
     51#define EEH_ERR_FUNC_DMA_WR_ADDR	16	/* DMA write	*/
     52#define EEH_ERR_FUNC_DMA_WR_DATA	17
     53#define EEH_ERR_FUNC_DMA_WR_MASTER	18
     54#define EEH_ERR_FUNC_DMA_WR_TARGET	19
     55#define EEH_ERR_FUNC_MAX		19
     56
     57#endif /* _ASM_POWERPC_EEH_H */