cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dawr.c (2652B)

      1// SPDX-License-Identifier: GPL-2.0+
      2/*
      3 * DAWR infrastructure
      4 *
      5 * Copyright 2019, Michael Neuling, IBM Corporation.
      6 */
      7
      8#include <linux/types.h>
      9#include <linux/export.h>
     10#include <linux/fs.h>
     11#include <linux/debugfs.h>
     12#include <asm/machdep.h>
     13#include <asm/hvcall.h>
     14
     15bool dawr_force_enable;
     16EXPORT_SYMBOL_GPL(dawr_force_enable);
     17
     18int set_dawr(int nr, struct arch_hw_breakpoint *brk)
     19{
     20	unsigned long dawr, dawrx, mrd;
     21
     22	dawr = brk->address;
     23
     24	dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE))
     25		<< (63 - 58);
     26	dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) << (63 - 59);
     27	dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) >> 3;
     28	/*
     29	 * DAWR length is stored in field MDR bits 48:53.  Matches range in
     30	 * doublewords (64 bits) biased by -1 eg. 0b000000=1DW and
     31	 * 0b111111=64DW.
     32	 * brk->hw_len is in bytes.
     33	 * This aligns up to double word size, shifts and does the bias.
     34	 */
     35	mrd = ((brk->hw_len + 7) >> 3) - 1;
     36	dawrx |= (mrd & 0x3f) << (63 - 53);
     37
     38	if (ppc_md.set_dawr)
     39		return ppc_md.set_dawr(nr, dawr, dawrx);
     40
     41	if (nr == 0) {
     42		mtspr(SPRN_DAWR0, dawr);
     43		mtspr(SPRN_DAWRX0, dawrx);
     44	} else {
     45		mtspr(SPRN_DAWR1, dawr);
     46		mtspr(SPRN_DAWRX1, dawrx);
     47	}
     48
     49	return 0;
     50}
     51
     52static void disable_dawrs_cb(void *info)
     53{
     54	struct arch_hw_breakpoint null_brk = {0};
     55	int i;
     56
     57	for (i = 0; i < nr_wp_slots(); i++)
     58		set_dawr(i, &null_brk);
     59}
     60
     61static ssize_t dawr_write_file_bool(struct file *file,
     62				    const char __user *user_buf,
     63				    size_t count, loff_t *ppos)
     64{
     65	struct arch_hw_breakpoint null_brk = {0};
     66	size_t rc;
     67
     68	/* Send error to user if they hypervisor won't allow us to write DAWR */
     69	if (!dawr_force_enable &&
     70	    firmware_has_feature(FW_FEATURE_LPAR) &&
     71	    set_dawr(0, &null_brk) != H_SUCCESS)
     72		return -ENODEV;
     73
     74	rc = debugfs_write_file_bool(file, user_buf, count, ppos);
     75	if (rc)
     76		return rc;
     77
     78	/* If we are clearing, make sure all CPUs have the DAWR cleared */
     79	if (!dawr_force_enable)
     80		smp_call_function(disable_dawrs_cb, NULL, 0);
     81
     82	return rc;
     83}
     84
     85static const struct file_operations dawr_enable_fops = {
     86	.read =		debugfs_read_file_bool,
     87	.write =	dawr_write_file_bool,
     88	.open =		simple_open,
     89	.llseek =	default_llseek,
     90};
     91
     92static int __init dawr_force_setup(void)
     93{
     94	if (cpu_has_feature(CPU_FTR_DAWR)) {
     95		/* Don't setup sysfs file for user control on P8 */
     96		dawr_force_enable = true;
     97		return 0;
     98	}
     99
    100	if (PVR_VER(mfspr(SPRN_PVR)) == PVR_POWER9) {
    101		/* Turn DAWR off by default, but allow admin to turn it on */
    102		debugfs_create_file_unsafe("dawr_enable_dangerous", 0600,
    103					   arch_debugfs_dir,
    104					   &dawr_force_enable,
    105					   &dawr_enable_fops);
    106	}
    107	return 0;
    108}
    109arch_initcall(dawr_force_setup);