cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pq2.c (1799B)

      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * Common PowerQUICC II code.
      4 *
      5 * Author: Scott Wood <scottwood@freescale.com>
      6 * Copyright (c) 2007 Freescale Semiconductor
      7 *
      8 * Based on code by Vitaly Bordug <vbordug@ru.mvista.com>
      9 * pq2_restart fix by Wade Farnsworth <wfarnsworth@mvista.com>
     10 * Copyright (c) 2006 MontaVista Software, Inc.
     11 */
     12
     13#include <linux/kprobes.h>
     14
     15#include <asm/cpm2.h>
     16#include <asm/io.h>
     17#include <asm/pci-bridge.h>
     18
     19#include <platforms/82xx/pq2.h>
     20
     21#define RMR_CSRE 0x00000001
     22
     23void __noreturn pq2_restart(char *cmd)
     24{
     25	local_irq_disable();
     26	setbits32(&cpm2_immr->im_clkrst.car_rmr, RMR_CSRE);
     27
     28	/* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */
     29	mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR));
     30	in_8(&cpm2_immr->im_clkrst.res[0]);
     31
     32	panic("Restart failed\n");
     33}
     34NOKPROBE_SYMBOL(pq2_restart)
     35
     36#ifdef CONFIG_PCI
     37static int pq2_pci_exclude_device(struct pci_controller *hose,
     38                                  u_char bus, u8 devfn)
     39{
     40	if (bus == 0 && PCI_SLOT(devfn) == 0)
     41		return PCIBIOS_DEVICE_NOT_FOUND;
     42	else
     43		return PCIBIOS_SUCCESSFUL;
     44}
     45
     46static void __init pq2_pci_add_bridge(struct device_node *np)
     47{
     48	struct pci_controller *hose;
     49	struct resource r;
     50
     51	if (of_address_to_resource(np, 0, &r) || r.end - r.start < 0x10b)
     52		goto err;
     53
     54	pci_add_flags(PCI_REASSIGN_ALL_BUS);
     55
     56	hose = pcibios_alloc_controller(np);
     57	if (!hose)
     58		return;
     59
     60	hose->dn = np;
     61
     62	setup_indirect_pci(hose, r.start + 0x100, r.start + 0x104, 0);
     63	pci_process_bridge_OF_ranges(hose, np, 1);
     64
     65	return;
     66
     67err:
     68	printk(KERN_ERR "No valid PCI reg property in device tree\n");
     69}
     70
     71void __init pq2_init_pci(void)
     72{
     73	struct device_node *np;
     74
     75	ppc_md.pci_exclude_device = pq2_pci_exclude_device;
     76
     77	for_each_compatible_node(np, NULL, "fsl,pq2-pci")
     78		pq2_pci_add_bridge(np);
     79}
     80#endif