cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pq2ads-pci-pic.c (3722B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * PQ2 ADS-style PCI interrupt controller
      4 *
      5 * Copyright 2007 Freescale Semiconductor, Inc.
      6 * Author: Scott Wood <scottwood@freescale.com>
      7 *
      8 * Loosely based on mpc82xx ADS support by Vitaly Bordug <vbordug@ru.mvista.com>
      9 * Copyright (c) 2006 MontaVista Software, Inc.
     10 */
     11
     12#include <linux/init.h>
     13#include <linux/spinlock.h>
     14#include <linux/irq.h>
     15#include <linux/types.h>
     16#include <linux/slab.h>
     17#include <linux/of_irq.h>
     18
     19#include <asm/io.h>
     20#include <asm/cpm2.h>
     21
     22#include "pq2.h"
     23
     24static DEFINE_RAW_SPINLOCK(pci_pic_lock);
     25
     26struct pq2ads_pci_pic {
     27	struct device_node *node;
     28	struct irq_domain *host;
     29
     30	struct {
     31		u32 stat;
     32		u32 mask;
     33	} __iomem *regs;
     34};
     35
     36#define NUM_IRQS 32
     37
     38static void pq2ads_pci_mask_irq(struct irq_data *d)
     39{
     40	struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d);
     41	int irq = NUM_IRQS - irqd_to_hwirq(d) - 1;
     42
     43	if (irq != -1) {
     44		unsigned long flags;
     45		raw_spin_lock_irqsave(&pci_pic_lock, flags);
     46
     47		setbits32(&priv->regs->mask, 1 << irq);
     48		mb();
     49
     50		raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
     51	}
     52}
     53
     54static void pq2ads_pci_unmask_irq(struct irq_data *d)
     55{
     56	struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d);
     57	int irq = NUM_IRQS - irqd_to_hwirq(d) - 1;
     58
     59	if (irq != -1) {
     60		unsigned long flags;
     61
     62		raw_spin_lock_irqsave(&pci_pic_lock, flags);
     63		clrbits32(&priv->regs->mask, 1 << irq);
     64		raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
     65	}
     66}
     67
     68static struct irq_chip pq2ads_pci_ic = {
     69	.name = "PQ2 ADS PCI",
     70	.irq_mask = pq2ads_pci_mask_irq,
     71	.irq_mask_ack = pq2ads_pci_mask_irq,
     72	.irq_ack = pq2ads_pci_mask_irq,
     73	.irq_unmask = pq2ads_pci_unmask_irq,
     74	.irq_enable = pq2ads_pci_unmask_irq,
     75	.irq_disable = pq2ads_pci_mask_irq
     76};
     77
     78static void pq2ads_pci_irq_demux(struct irq_desc *desc)
     79{
     80	struct pq2ads_pci_pic *priv = irq_desc_get_handler_data(desc);
     81	u32 stat, mask, pend;
     82	int bit;
     83
     84	for (;;) {
     85		stat = in_be32(&priv->regs->stat);
     86		mask = in_be32(&priv->regs->mask);
     87
     88		pend = stat & ~mask;
     89
     90		if (!pend)
     91			break;
     92
     93		for (bit = 0; pend != 0; ++bit, pend <<= 1) {
     94			if (pend & 0x80000000)
     95				generic_handle_domain_irq(priv->host, bit);
     96		}
     97	}
     98}
     99
    100static int pci_pic_host_map(struct irq_domain *h, unsigned int virq,
    101			    irq_hw_number_t hw)
    102{
    103	irq_set_status_flags(virq, IRQ_LEVEL);
    104	irq_set_chip_data(virq, h->host_data);
    105	irq_set_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq);
    106	return 0;
    107}
    108
    109static const struct irq_domain_ops pci_pic_host_ops = {
    110	.map = pci_pic_host_map,
    111};
    112
    113int __init pq2ads_pci_init_irq(void)
    114{
    115	struct pq2ads_pci_pic *priv;
    116	struct irq_domain *host;
    117	struct device_node *np;
    118	int ret = -ENODEV;
    119	int irq;
    120
    121	np = of_find_compatible_node(NULL, NULL, "fsl,pq2ads-pci-pic");
    122	if (!np) {
    123		printk(KERN_ERR "No pci pic node in device tree.\n");
    124		goto out;
    125	}
    126
    127	irq = irq_of_parse_and_map(np, 0);
    128	if (!irq) {
    129		printk(KERN_ERR "No interrupt in pci pic node.\n");
    130		goto out_put_node;
    131	}
    132
    133	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
    134	if (!priv) {
    135		ret = -ENOMEM;
    136		goto out_unmap_irq;
    137	}
    138
    139	/* PCI interrupt controller registers: status and mask */
    140	priv->regs = of_iomap(np, 0);
    141	if (!priv->regs) {
    142		printk(KERN_ERR "Cannot map PCI PIC registers.\n");
    143		goto out_free_kmalloc;
    144	}
    145
    146	/* mask all PCI interrupts */
    147	out_be32(&priv->regs->mask, ~0);
    148	mb();
    149
    150	host = irq_domain_add_linear(np, NUM_IRQS, &pci_pic_host_ops, priv);
    151	if (!host) {
    152		ret = -ENOMEM;
    153		goto out_unmap_regs;
    154	}
    155
    156	priv->host = host;
    157	irq_set_handler_data(irq, priv);
    158	irq_set_chained_handler(irq, pq2ads_pci_irq_demux);
    159	ret = 0;
    160	goto out_put_node;
    161
    162out_unmap_regs:
    163	iounmap(priv->regs);
    164out_free_kmalloc:
    165	kfree(priv);
    166out_unmap_irq:
    167	irq_dispose_mapping(irq);
    168out_put_node:
    169	of_node_put(np);
    170out:
    171	return ret;
    172}