pq2fads.c (5051B)
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * PQ2FADS board support 4 * 5 * Copyright 2007 Freescale Semiconductor, Inc. 6 * Author: Scott Wood <scottwood@freescale.com> 7 * 8 * Loosely based on mp82xx ADS support by Vitaly Bordug <vbordug@ru.mvista.com> 9 * Copyright (c) 2006 MontaVista Software, Inc. 10 */ 11 12#include <linux/init.h> 13#include <linux/interrupt.h> 14#include <linux/fsl_devices.h> 15#include <linux/of_address.h> 16#include <linux/of_fdt.h> 17#include <linux/of_platform.h> 18 19#include <asm/io.h> 20#include <asm/cpm2.h> 21#include <asm/udbg.h> 22#include <asm/machdep.h> 23#include <asm/time.h> 24 25#include <sysdev/fsl_soc.h> 26#include <sysdev/cpm2_pic.h> 27 28#include "pq2ads.h" 29#include "pq2.h" 30 31static void __init pq2fads_pic_init(void) 32{ 33 struct device_node *np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic"); 34 if (!np) { 35 printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n"); 36 return; 37 } 38 39 cpm2_pic_init(np); 40 of_node_put(np); 41 42 /* Initialize stuff for the 82xx CPLD IC and install demux */ 43 pq2ads_pci_init_irq(); 44} 45 46struct cpm_pin { 47 int port, pin, flags; 48}; 49 50static struct cpm_pin pq2fads_pins[] = { 51 /* SCC1 */ 52 {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, 53 {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 54 55 /* SCC2 */ 56 {3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 57 {3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 58 59 /* FCC2 */ 60 {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 61 {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 62 {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 63 {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 64 {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 65 {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 66 {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 67 {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 68 {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 69 {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 70 {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 71 {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, 72 {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 73 {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 74 {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 75 {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 76 77 /* FCC3 */ 78 {1, 4, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 79 {1, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 80 {1, 6, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 81 {1, 7, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 82 {1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 83 {1, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 84 {1, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 85 {1, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 86 {1, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 87 {1, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 88 {1, 14, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 89 {1, 15, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 90 {1, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 91 {1, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 92 {2, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 93 {2, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 94}; 95 96static void __init init_ioports(void) 97{ 98 int i; 99 100 for (i = 0; i < ARRAY_SIZE(pq2fads_pins); i++) { 101 struct cpm_pin *pin = &pq2fads_pins[i]; 102 cpm2_set_pin(pin->port, pin->pin, pin->flags); 103 } 104 105 cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX); 106 cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX); 107 cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX); 108 cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX); 109 cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX); 110 cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX); 111 cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK15, CPM_CLK_RX); 112 cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK16, CPM_CLK_TX); 113} 114 115static void __init pq2fads_setup_arch(void) 116{ 117 struct device_node *np; 118 __be32 __iomem *bcsr; 119 120 if (ppc_md.progress) 121 ppc_md.progress("pq2fads_setup_arch()", 0); 122 123 cpm2_reset(); 124 125 np = of_find_compatible_node(NULL, NULL, "fsl,pq2fads-bcsr"); 126 if (!np) { 127 printk(KERN_ERR "No fsl,pq2fads-bcsr in device tree\n"); 128 return; 129 } 130 131 bcsr = of_iomap(np, 0); 132 of_node_put(np); 133 if (!bcsr) { 134 printk(KERN_ERR "Cannot map BCSR registers\n"); 135 return; 136 } 137 138 /* Enable the serial and ethernet ports */ 139 140 clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN); 141 setbits32(&bcsr[1], BCSR1_FETH_RST); 142 143 clrbits32(&bcsr[3], BCSR3_FETHIEN2); 144 setbits32(&bcsr[3], BCSR3_FETH2_RST); 145 146 iounmap(bcsr); 147 148 init_ioports(); 149 150 /* Enable external IRQs */ 151 clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_siumcr, 0x0c000000); 152 153 if (ppc_md.progress) 154 ppc_md.progress("pq2fads_setup_arch(), finish", 0); 155} 156 157/* 158 * Called very early, device-tree isn't unflattened 159 */ 160static int __init pq2fads_probe(void) 161{ 162 return of_machine_is_compatible("fsl,pq2fads"); 163} 164 165static const struct of_device_id of_bus_ids[] __initconst = { 166 { .name = "soc", }, 167 { .name = "cpm", }, 168 { .name = "localbus", }, 169 {}, 170}; 171 172static int __init declare_of_platform_devices(void) 173{ 174 /* Publish the QE devices */ 175 of_platform_bus_probe(NULL, of_bus_ids, NULL); 176 return 0; 177} 178machine_device_initcall(pq2fads, declare_of_platform_devices); 179 180define_machine(pq2fads) 181{ 182 .name = "Freescale PQ2FADS", 183 .probe = pq2fads_probe, 184 .setup_arch = pq2fads_setup_arch, 185 .discover_phbs = pq2_init_pci, 186 .init_IRQ = pq2fads_pic_init, 187 .get_irq = cpm2_get_irq, 188 .calibrate_decr = generic_calibrate_decr, 189 .restart = pq2_restart, 190 .progress = udbg_progress, 191};