cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

mpc83xx.h (2959B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2#ifndef __MPC83XX_H__
      3#define __MPC83XX_H__
      4
      5#include <linux/init.h>
      6#include <linux/device.h>
      7#include <asm/pci-bridge.h>
      8
      9/* System Clock Control Register */
     10#define MPC83XX_SCCR_OFFS          0xA08
     11#define MPC83XX_SCCR_USB_MASK      0x00f00000
     12#define MPC83XX_SCCR_USB_MPHCM_11  0x00c00000
     13#define MPC83XX_SCCR_USB_MPHCM_01  0x00400000
     14#define MPC83XX_SCCR_USB_MPHCM_10  0x00800000
     15#define MPC83XX_SCCR_USB_DRCM_11   0x00300000
     16#define MPC83XX_SCCR_USB_DRCM_01   0x00100000
     17#define MPC83XX_SCCR_USB_DRCM_10   0x00200000
     18#define MPC8315_SCCR_USB_MASK      0x00c00000
     19#define MPC8315_SCCR_USB_DRCM_11   0x00c00000
     20#define MPC8315_SCCR_USB_DRCM_01   0x00400000
     21#define MPC837X_SCCR_USB_DRCM_11   0x00c00000
     22
     23/* system i/o configuration register low */
     24#define MPC83XX_SICRL_OFFS         0x114
     25#define MPC834X_SICRL_USB_MASK     0x60000000
     26#define MPC834X_SICRL_USB0         0x20000000
     27#define MPC834X_SICRL_USB1         0x40000000
     28#define MPC831X_SICRL_USB_MASK     0x00000c00
     29#define MPC831X_SICRL_USB_ULPI     0x00000800
     30#define MPC8315_SICRL_USB_MASK     0x000000fc
     31#define MPC8315_SICRL_USB_ULPI     0x00000054
     32#define MPC837X_SICRL_USB_MASK     0xf0000000
     33#define MPC837X_SICRL_USB_ULPI     0x50000000
     34#define MPC837X_SICRL_USBB_MASK    0x30000000
     35#define MPC837X_SICRL_SD           0x20000000
     36
     37/* system i/o configuration register high */
     38#define MPC83XX_SICRH_OFFS         0x118
     39#define MPC8308_SICRH_USB_MASK     0x000c0000
     40#define MPC8308_SICRH_USB_ULPI     0x00040000
     41#define MPC834X_SICRH_USB_UTMI     0x00020000
     42#define MPC831X_SICRH_USB_MASK     0x000000e0
     43#define MPC831X_SICRH_USB_ULPI     0x000000a0
     44#define MPC8315_SICRH_USB_MASK     0x0000ff00
     45#define MPC8315_SICRH_USB_ULPI     0x00000000
     46#define MPC837X_SICRH_SPI_MASK     0x00000003
     47#define MPC837X_SICRH_SD           0x00000001
     48
     49/* USB Control Register */
     50#define FSL_USB2_CONTROL_OFFS      0x500
     51#define CONTROL_UTMI_PHY_EN        0x00000200
     52#define CONTROL_REFSEL_24MHZ       0x00000040
     53#define CONTROL_REFSEL_48MHZ       0x00000080
     54#define CONTROL_PHY_CLK_SEL_ULPI   0x00000400
     55#define CONTROL_OTG_PORT           0x00000020
     56
     57/* USB PORTSC Registers */
     58#define FSL_USB2_PORTSC1_OFFS      0x184
     59#define FSL_USB2_PORTSC2_OFFS      0x188
     60#define PORTSCX_PTW_16BIT          0x10000000
     61#define PORTSCX_PTS_UTMI           0x00000000
     62#define PORTSCX_PTS_ULPI           0x80000000
     63
     64/*
     65 * Declaration for the various functions exported by the
     66 * mpc83xx_* files. Mostly for use by mpc83xx_setup
     67 */
     68
     69extern void __noreturn mpc83xx_restart(char *cmd);
     70extern long mpc83xx_time_init(void);
     71int __init mpc837x_usb_cfg(void);
     72int __init mpc834x_usb_cfg(void);
     73int __init mpc831x_usb_cfg(void);
     74extern void mpc83xx_ipic_init_IRQ(void);
     75
     76#ifdef CONFIG_PCI
     77extern void mpc83xx_setup_pci(void);
     78#else
     79#define mpc83xx_setup_pci	NULL
     80#endif
     81
     82extern int mpc83xx_declare_of_platform_devices(void);
     83extern void mpc83xx_setup_arch(void);
     84
     85#endif				/* __MPC83XX_H__ */