cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mpc85xx_ads.c (4706B)

      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * MPC85xx setup and early boot code plus other random bits.
      4 *
      5 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
      6 *
      7 * Copyright 2005 Freescale Semiconductor Inc.
      8 */
      9
     10#include <linux/stddef.h>
     11#include <linux/kernel.h>
     12#include <linux/pci.h>
     13#include <linux/kdev_t.h>
     14#include <linux/delay.h>
     15#include <linux/seq_file.h>
     16#include <linux/of_platform.h>
     17
     18#include <asm/time.h>
     19#include <asm/machdep.h>
     20#include <asm/pci-bridge.h>
     21#include <asm/mpic.h>
     22#include <mm/mmu_decl.h>
     23#include <asm/udbg.h>
     24
     25#include <sysdev/fsl_soc.h>
     26#include <sysdev/fsl_pci.h>
     27
     28#ifdef CONFIG_CPM2
     29#include <asm/cpm2.h>
     30#include <sysdev/cpm2_pic.h>
     31#endif
     32
     33#include "mpc85xx.h"
     34
     35static void __init mpc85xx_ads_pic_init(void)
     36{
     37	struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
     38			0, 256, " OpenPIC  ");
     39	BUG_ON(mpic == NULL);
     40	mpic_init(mpic);
     41
     42	mpc85xx_cpm2_pic_init();
     43}
     44
     45/*
     46 * Setup the architecture
     47 */
     48#ifdef CONFIG_CPM2
     49struct cpm_pin {
     50	int port, pin, flags;
     51};
     52
     53static const struct cpm_pin mpc8560_ads_pins[] = {
     54	/* SCC1 */
     55	{3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
     56	{3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
     57	{3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
     58
     59	/* SCC2 */
     60	{2, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
     61	{2, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
     62	{3, 26, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
     63	{3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
     64	{3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
     65
     66	/* FCC2 */
     67	{1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
     68	{1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
     69	{1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
     70	{1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
     71	{1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
     72	{1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
     73	{1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
     74	{1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
     75	{1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
     76	{1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
     77	{1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
     78	{1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
     79	{1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
     80	{1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
     81	{2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK14 */
     82	{2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK13 */
     83
     84	/* FCC3 */
     85	{1, 4, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
     86	{1, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
     87	{1, 6, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
     88	{1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
     89	{1, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
     90	{1, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
     91	{1, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
     92	{1, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
     93	{1, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
     94	{1, 14, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
     95	{1, 15, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
     96	{1, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
     97	{1, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
     98	{2, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK16 */
     99	{2, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK15 */
    100	{2, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
    101};
    102
    103static void __init init_ioports(void)
    104{
    105	int i;
    106
    107	for (i = 0; i < ARRAY_SIZE(mpc8560_ads_pins); i++) {
    108		const struct cpm_pin *pin = &mpc8560_ads_pins[i];
    109		cpm2_set_pin(pin->port, pin->pin, pin->flags);
    110	}
    111
    112	cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
    113	cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
    114	cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
    115	cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
    116	cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
    117	cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
    118	cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK15, CPM_CLK_RX);
    119	cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK16, CPM_CLK_TX);
    120}
    121#endif
    122
    123static void __init mpc85xx_ads_setup_arch(void)
    124{
    125	if (ppc_md.progress)
    126		ppc_md.progress("mpc85xx_ads_setup_arch()", 0);
    127
    128#ifdef CONFIG_CPM2
    129	cpm2_reset();
    130	init_ioports();
    131#endif
    132
    133	fsl_pci_assign_primary();
    134}
    135
    136static void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
    137{
    138	uint pvid, svid, phid1;
    139
    140	pvid = mfspr(SPRN_PVR);
    141	svid = mfspr(SPRN_SVR);
    142
    143	seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
    144	seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
    145	seq_printf(m, "SVR\t\t: 0x%x\n", svid);
    146
    147	/* Display cpu Pll setting */
    148	phid1 = mfspr(SPRN_HID1);
    149	seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
    150}
    151
    152machine_arch_initcall(mpc85xx_ads, mpc85xx_common_publish_devices);
    153
    154/*
    155 * Called very early, device-tree isn't unflattened
    156 */
    157static int __init mpc85xx_ads_probe(void)
    158{
    159	return of_machine_is_compatible("MPC85xxADS");
    160}
    161
    162define_machine(mpc85xx_ads) {
    163	.name			= "MPC85xx ADS",
    164	.probe			= mpc85xx_ads_probe,
    165	.setup_arch		= mpc85xx_ads_setup_arch,
    166	.init_IRQ		= mpc85xx_ads_pic_init,
    167	.show_cpuinfo		= mpc85xx_ads_show_cpuinfo,
    168	.get_irq		= mpic_get_irq,
    169	.calibrate_decr		= generic_calibrate_decr,
    170	.progress		= udbg_progress,
    171};