mpc85xx_rdb.c (8010B)
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * MPC85xx RDB Board Setup 4 * 5 * Copyright 2009,2012-2013 Freescale Semiconductor Inc. 6 */ 7 8#include <linux/stddef.h> 9#include <linux/kernel.h> 10#include <linux/pci.h> 11#include <linux/kdev_t.h> 12#include <linux/delay.h> 13#include <linux/seq_file.h> 14#include <linux/interrupt.h> 15#include <linux/of_platform.h> 16#include <linux/fsl/guts.h> 17 18#include <asm/time.h> 19#include <asm/machdep.h> 20#include <asm/pci-bridge.h> 21#include <mm/mmu_decl.h> 22#include <asm/udbg.h> 23#include <asm/mpic.h> 24#include <soc/fsl/qe/qe.h> 25 26#include <sysdev/fsl_soc.h> 27#include <sysdev/fsl_pci.h> 28#include "smp.h" 29 30#include "mpc85xx.h" 31 32#undef DEBUG 33 34#ifdef DEBUG 35#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args) 36#else 37#define DBG(fmt, args...) 38#endif 39 40 41void __init mpc85xx_rdb_pic_init(void) 42{ 43 struct mpic *mpic; 44 45 if (of_machine_is_compatible("fsl,MPC85XXRDB-CAMP")) { 46 mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET | 47 MPIC_BIG_ENDIAN | 48 MPIC_SINGLE_DEST_CPU, 49 0, 256, " OpenPIC "); 50 } else { 51 mpic = mpic_alloc(NULL, 0, 52 MPIC_BIG_ENDIAN | 53 MPIC_SINGLE_DEST_CPU, 54 0, 256, " OpenPIC "); 55 } 56 57 BUG_ON(mpic == NULL); 58 mpic_init(mpic); 59} 60 61/* 62 * Setup the architecture 63 */ 64static void __init mpc85xx_rdb_setup_arch(void) 65{ 66 if (ppc_md.progress) 67 ppc_md.progress("mpc85xx_rdb_setup_arch()", 0); 68 69 mpc85xx_smp_init(); 70 71 fsl_pci_assign_primary(); 72 73#ifdef CONFIG_QUICC_ENGINE 74 mpc85xx_qe_par_io_init(); 75#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) 76 if (machine_is(p1025_rdb)) { 77 struct device_node *np; 78 79 struct ccsr_guts __iomem *guts; 80 81 np = of_find_node_by_name(NULL, "global-utilities"); 82 if (np) { 83 guts = of_iomap(np, 0); 84 if (!guts) { 85 86 pr_err("mpc85xx-rdb: could not map global utilities register\n"); 87 88 } else { 89 /* P1025 has pins muxed for QE and other functions. To 90 * enable QE UEC mode, we need to set bit QE0 for UCC1 91 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 92 * and QE12 for QE MII management singals in PMUXCR 93 * register. 94 */ 95 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | 96 MPC85xx_PMUXCR_QE(3) | 97 MPC85xx_PMUXCR_QE(9) | 98 MPC85xx_PMUXCR_QE(12)); 99 iounmap(guts); 100 } 101 of_node_put(np); 102 } 103 104 } 105#endif 106#endif /* CONFIG_QUICC_ENGINE */ 107 108 printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n"); 109} 110 111machine_arch_initcall(p2020_rdb, mpc85xx_common_publish_devices); 112machine_arch_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices); 113machine_arch_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices); 114machine_arch_initcall(p1020_rdb, mpc85xx_common_publish_devices); 115machine_arch_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices); 116machine_arch_initcall(p1020_rdb_pd, mpc85xx_common_publish_devices); 117machine_arch_initcall(p1020_utm_pc, mpc85xx_common_publish_devices); 118machine_arch_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices); 119machine_arch_initcall(p1025_rdb, mpc85xx_common_publish_devices); 120machine_arch_initcall(p1024_rdb, mpc85xx_common_publish_devices); 121 122/* 123 * Called very early, device-tree isn't unflattened 124 */ 125static int __init p2020_rdb_probe(void) 126{ 127 if (of_machine_is_compatible("fsl,P2020RDB")) 128 return 1; 129 return 0; 130} 131 132static int __init p1020_rdb_probe(void) 133{ 134 if (of_machine_is_compatible("fsl,P1020RDB")) 135 return 1; 136 return 0; 137} 138 139static int __init p1020_rdb_pc_probe(void) 140{ 141 return of_machine_is_compatible("fsl,P1020RDB-PC"); 142} 143 144static int __init p1020_rdb_pd_probe(void) 145{ 146 return of_machine_is_compatible("fsl,P1020RDB-PD"); 147} 148 149static int __init p1021_rdb_pc_probe(void) 150{ 151 if (of_machine_is_compatible("fsl,P1021RDB-PC")) 152 return 1; 153 return 0; 154} 155 156static int __init p2020_rdb_pc_probe(void) 157{ 158 if (of_machine_is_compatible("fsl,P2020RDB-PC")) 159 return 1; 160 return 0; 161} 162 163static int __init p1025_rdb_probe(void) 164{ 165 return of_machine_is_compatible("fsl,P1025RDB"); 166} 167 168static int __init p1020_mbg_pc_probe(void) 169{ 170 return of_machine_is_compatible("fsl,P1020MBG-PC"); 171} 172 173static int __init p1020_utm_pc_probe(void) 174{ 175 return of_machine_is_compatible("fsl,P1020UTM-PC"); 176} 177 178static int __init p1024_rdb_probe(void) 179{ 180 return of_machine_is_compatible("fsl,P1024RDB"); 181} 182 183define_machine(p2020_rdb) { 184 .name = "P2020 RDB", 185 .probe = p2020_rdb_probe, 186 .setup_arch = mpc85xx_rdb_setup_arch, 187 .init_IRQ = mpc85xx_rdb_pic_init, 188#ifdef CONFIG_PCI 189 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 190 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 191#endif 192 .get_irq = mpic_get_irq, 193 .calibrate_decr = generic_calibrate_decr, 194 .progress = udbg_progress, 195}; 196 197define_machine(p1020_rdb) { 198 .name = "P1020 RDB", 199 .probe = p1020_rdb_probe, 200 .setup_arch = mpc85xx_rdb_setup_arch, 201 .init_IRQ = mpc85xx_rdb_pic_init, 202#ifdef CONFIG_PCI 203 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 204 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 205#endif 206 .get_irq = mpic_get_irq, 207 .calibrate_decr = generic_calibrate_decr, 208 .progress = udbg_progress, 209}; 210 211define_machine(p1021_rdb_pc) { 212 .name = "P1021 RDB-PC", 213 .probe = p1021_rdb_pc_probe, 214 .setup_arch = mpc85xx_rdb_setup_arch, 215 .init_IRQ = mpc85xx_rdb_pic_init, 216#ifdef CONFIG_PCI 217 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 218 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 219#endif 220 .get_irq = mpic_get_irq, 221 .calibrate_decr = generic_calibrate_decr, 222 .progress = udbg_progress, 223}; 224 225define_machine(p2020_rdb_pc) { 226 .name = "P2020RDB-PC", 227 .probe = p2020_rdb_pc_probe, 228 .setup_arch = mpc85xx_rdb_setup_arch, 229 .init_IRQ = mpc85xx_rdb_pic_init, 230#ifdef CONFIG_PCI 231 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 232 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 233#endif 234 .get_irq = mpic_get_irq, 235 .calibrate_decr = generic_calibrate_decr, 236 .progress = udbg_progress, 237}; 238 239define_machine(p1025_rdb) { 240 .name = "P1025 RDB", 241 .probe = p1025_rdb_probe, 242 .setup_arch = mpc85xx_rdb_setup_arch, 243 .init_IRQ = mpc85xx_rdb_pic_init, 244#ifdef CONFIG_PCI 245 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 246 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 247#endif 248 .get_irq = mpic_get_irq, 249 .calibrate_decr = generic_calibrate_decr, 250 .progress = udbg_progress, 251}; 252 253define_machine(p1020_mbg_pc) { 254 .name = "P1020 MBG-PC", 255 .probe = p1020_mbg_pc_probe, 256 .setup_arch = mpc85xx_rdb_setup_arch, 257 .init_IRQ = mpc85xx_rdb_pic_init, 258#ifdef CONFIG_PCI 259 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 260 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 261#endif 262 .get_irq = mpic_get_irq, 263 .calibrate_decr = generic_calibrate_decr, 264 .progress = udbg_progress, 265}; 266 267define_machine(p1020_utm_pc) { 268 .name = "P1020 UTM-PC", 269 .probe = p1020_utm_pc_probe, 270 .setup_arch = mpc85xx_rdb_setup_arch, 271 .init_IRQ = mpc85xx_rdb_pic_init, 272#ifdef CONFIG_PCI 273 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 274 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 275#endif 276 .get_irq = mpic_get_irq, 277 .calibrate_decr = generic_calibrate_decr, 278 .progress = udbg_progress, 279}; 280 281define_machine(p1020_rdb_pc) { 282 .name = "P1020RDB-PC", 283 .probe = p1020_rdb_pc_probe, 284 .setup_arch = mpc85xx_rdb_setup_arch, 285 .init_IRQ = mpc85xx_rdb_pic_init, 286#ifdef CONFIG_PCI 287 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 288 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 289#endif 290 .get_irq = mpic_get_irq, 291 .calibrate_decr = generic_calibrate_decr, 292 .progress = udbg_progress, 293}; 294 295define_machine(p1020_rdb_pd) { 296 .name = "P1020RDB-PD", 297 .probe = p1020_rdb_pd_probe, 298 .setup_arch = mpc85xx_rdb_setup_arch, 299 .init_IRQ = mpc85xx_rdb_pic_init, 300#ifdef CONFIG_PCI 301 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 302 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 303#endif 304 .get_irq = mpic_get_irq, 305 .calibrate_decr = generic_calibrate_decr, 306 .progress = udbg_progress, 307}; 308 309define_machine(p1024_rdb) { 310 .name = "P1024 RDB", 311 .probe = p1024_rdb_probe, 312 .setup_arch = mpc85xx_rdb_setup_arch, 313 .init_IRQ = mpc85xx_rdb_pic_init, 314#ifdef CONFIG_PCI 315 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 316 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 317#endif 318 .get_irq = mpic_get_irq, 319 .calibrate_decr = generic_calibrate_decr, 320 .progress = udbg_progress, 321};