cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

Kconfig (4745B)


      1# SPDX-License-Identifier: GPL-2.0
      2config CPM1
      3	bool
      4	select CPM
      5
      6choice
      7	prompt "8xx Machine Type"
      8	depends on PPC_8xx
      9	default MPC885ADS
     10
     11config MPC8XXFADS
     12	bool "FADS"
     13
     14config MPC86XADS
     15	bool "MPC86XADS"
     16	select CPM1
     17	help
     18	  MPC86x Application Development System by Freescale Semiconductor.
     19	  The MPC86xADS is meant to serve as a platform for s/w and h/w
     20	  development around the MPC86X processor families.
     21
     22config MPC885ADS
     23	bool "MPC885ADS"
     24	select CPM1
     25	select OF_DYNAMIC
     26	help
     27	  Freescale Semiconductor MPC885 Application Development System (ADS).
     28	  Also known as DUET.
     29	  The MPC885ADS is meant to serve as a platform for s/w and h/w
     30	  development around the MPC885 processor family.
     31
     32config PPC_EP88XC
     33	bool "Embedded Planet EP88xC (a.k.a. CWH-PPC-885XN-VE)"
     34	select CPM1
     35	help
     36	  This enables support for the Embedded Planet EP88xC board.
     37
     38	  This board is also resold by Freescale as the QUICCStart
     39	  MPC885 Evaluation System and/or the CWH-PPC-885XN-VE.
     40
     41config PPC_ADDER875
     42	bool "Analogue & Micro Adder 875"
     43	select CPM1
     44	help
     45	  This enables support for the Analogue & Micro Adder 875
     46	  board.
     47
     48config TQM8XX
     49	bool "TQM8XX"
     50	select CPM1
     51	help
     52	  support for the mpc8xx based boards from TQM.
     53
     54endchoice
     55
     56menu "Freescale Ethernet driver platform-specific options"
     57	depends on (FS_ENET && MPC885ADS)
     58
     59	config MPC8xx_SECOND_ETH
     60	bool "Second Ethernet channel"
     61	depends on MPC885ADS
     62	default y
     63	help
     64	  This enables support for second Ethernet on MPC885ADS and MPC86xADS boards.
     65	  The latter will use SCC1, for 885ADS you can select it below.
     66
     67	choice
     68		prompt "Second Ethernet channel"
     69		depends on MPC8xx_SECOND_ETH
     70		default MPC8xx_SECOND_ETH_FEC2
     71
     72		config MPC8xx_SECOND_ETH_FEC2
     73		bool "FEC2"
     74		depends on MPC885ADS
     75		help
     76		  Enable FEC2 to serve as 2-nd Ethernet channel. Note that SMC2
     77		  (often 2-nd UART) will not work if this is enabled.
     78
     79		config MPC8xx_SECOND_ETH_SCC3
     80		bool "SCC3"
     81		depends on MPC885ADS
     82		help
     83		  Enable SCC3 to serve as 2-nd Ethernet channel. Note that SMC1
     84		  (often 1-nd UART) will not work if this is enabled.
     85
     86	endchoice
     87
     88endmenu
     89
     90#
     91# MPC8xx Communication options
     92#
     93
     94menu "MPC8xx CPM Options"
     95	depends on PPC_8xx
     96
     97# This doesn't really belong here, but it is convenient to ask
     98# 8xx specific questions.
     99comment "Generic MPC8xx Options"
    100
    101config 8xx_GPIO
    102	bool "GPIO API Support"
    103	select GPIOLIB
    104	help
    105	  Saying Y here will cause the ports on an MPC8xx processor to be used
    106	  with the GPIO API.  If you say N here, the kernel needs less memory.
    107
    108	  If in doubt, say Y here.
    109
    110config 8xx_CPU15
    111	bool "CPU15 Silicon Errata"
    112	depends on !HUGETLB_PAGE
    113	default y
    114	help
    115	  This enables a workaround for erratum CPU15 on MPC8xx chips.
    116	  This bug can cause incorrect code execution under certain
    117	  circumstances.  This workaround adds some overhead (a TLB miss
    118	  every time execution crosses a page boundary), and you may wish
    119	  to disable it if you have worked around the bug in the compiler
    120	  (by not placing conditional branches or branches to LR or CTR
    121	  in the last word of a page, with a target of the last cache
    122	  line in the next page), or if you have used some other
    123	  workaround.
    124
    125	  If in doubt, say Y here.
    126
    127choice
    128	prompt "Microcode patch selection"
    129	default NO_UCODE_PATCH
    130	help
    131	  Help not implemented yet, coming soon.
    132
    133config NO_UCODE_PATCH
    134	bool "None"
    135
    136config USB_SOF_UCODE_PATCH
    137	bool "USB SOF patch"
    138	help
    139	  Help not implemented yet, coming soon.
    140
    141config I2C_SPI_UCODE_PATCH
    142	bool "I2C/SPI relocation patch"
    143	help
    144	  Help not implemented yet, coming soon.
    145
    146config I2C_SPI_SMC1_UCODE_PATCH
    147	bool "I2C/SPI/SMC1 relocation patch"
    148	help
    149	  Help not implemented yet, coming soon.
    150
    151config SMC_UCODE_PATCH
    152	bool "SMC relocation patch"
    153	help
    154	  This microcode relocates SMC1 and SMC2 parameter RAMs at
    155	  offset 0x1ec0 and 0x1fc0 to allow extended parameter RAM
    156	  for SCC3 and SCC4.
    157
    158endchoice
    159
    160config UCODE_PATCH
    161	bool
    162	default y
    163	depends on !NO_UCODE_PATCH
    164
    165menu "8xx advanced setup"
    166	depends on PPC_8xx
    167
    168config PIN_TLB
    169	bool "Pinned Kernel TLBs"
    170	depends on ADVANCED_OPTIONS
    171	help
    172	  On the 8xx, we have 32 instruction TLBs and 32 data TLBs. In each
    173	  table 4 TLBs can be pinned.
    174
    175	  It reduces the amount of usable TLBs to 28 (ie by 12%). That's the
    176	  reason why we make it selectable.
    177
    178	  This option does nothing, it just activate the selection of what
    179	  to pin.
    180
    181config PIN_TLB_DATA
    182	bool "Pinned TLB for DATA"
    183	depends on PIN_TLB
    184	default y
    185	help
    186	  This pins the first 32 Mbytes of memory with 8M pages.
    187
    188config PIN_TLB_IMMR
    189	bool "Pinned TLB for IMMR"
    190	depends on PIN_TLB
    191	default y
    192	help
    193	  This pins the IMMR area with a 512kbytes page. In case
    194	  CONFIG_PIN_TLB_DATA is also selected, it will reduce
    195	  CONFIG_PIN_TLB_DATA to 24 Mbytes.
    196
    197endmenu
    198
    199endmenu