cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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adder875.c (2864B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/* Analogue & Micro Adder MPC875 board support
      3 *
      4 * Author: Scott Wood <scottwood@freescale.com>
      5 *
      6 * Copyright (c) 2007 Freescale Semiconductor, Inc.
      7 */
      8
      9#include <linux/init.h>
     10#include <linux/fs_enet_pd.h>
     11#include <linux/of_platform.h>
     12
     13#include <asm/time.h>
     14#include <asm/machdep.h>
     15#include <asm/cpm1.h>
     16#include <asm/fs_pd.h>
     17#include <asm/udbg.h>
     18
     19#include "mpc8xx.h"
     20#include "pic.h"
     21
     22struct cpm_pin {
     23	int port, pin, flags;
     24};
     25
     26static __initdata struct cpm_pin adder875_pins[] = {
     27	/* SMC1 */
     28	{CPM_PORTB, 24, CPM_PIN_INPUT}, /* RX */
     29	{CPM_PORTB, 25, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
     30
     31	/* MII1 */
     32	{CPM_PORTA, 0, CPM_PIN_INPUT},
     33	{CPM_PORTA, 1, CPM_PIN_INPUT},
     34	{CPM_PORTA, 2, CPM_PIN_INPUT},
     35	{CPM_PORTA, 3, CPM_PIN_INPUT},
     36	{CPM_PORTA, 4, CPM_PIN_OUTPUT},
     37	{CPM_PORTA, 10, CPM_PIN_OUTPUT},
     38	{CPM_PORTA, 11, CPM_PIN_OUTPUT},
     39	{CPM_PORTB, 19, CPM_PIN_INPUT},
     40	{CPM_PORTB, 31, CPM_PIN_INPUT},
     41	{CPM_PORTC, 12, CPM_PIN_INPUT},
     42	{CPM_PORTC, 13, CPM_PIN_INPUT},
     43	{CPM_PORTE, 30, CPM_PIN_OUTPUT},
     44	{CPM_PORTE, 31, CPM_PIN_OUTPUT},
     45
     46	/* MII2 */
     47	{CPM_PORTE, 14, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
     48	{CPM_PORTE, 15, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
     49	{CPM_PORTE, 16, CPM_PIN_OUTPUT},
     50	{CPM_PORTE, 17, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
     51	{CPM_PORTE, 18, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
     52	{CPM_PORTE, 19, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
     53	{CPM_PORTE, 20, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
     54	{CPM_PORTE, 21, CPM_PIN_OUTPUT},
     55	{CPM_PORTE, 22, CPM_PIN_OUTPUT},
     56	{CPM_PORTE, 23, CPM_PIN_OUTPUT},
     57	{CPM_PORTE, 24, CPM_PIN_OUTPUT},
     58	{CPM_PORTE, 25, CPM_PIN_OUTPUT},
     59	{CPM_PORTE, 26, CPM_PIN_OUTPUT},
     60	{CPM_PORTE, 27, CPM_PIN_OUTPUT},
     61	{CPM_PORTE, 28, CPM_PIN_OUTPUT},
     62	{CPM_PORTE, 29, CPM_PIN_OUTPUT},
     63};
     64
     65static void __init init_ioports(void)
     66{
     67	int i;
     68
     69	for (i = 0; i < ARRAY_SIZE(adder875_pins); i++) {
     70		const struct cpm_pin *pin = &adder875_pins[i];
     71		cpm1_set_pin(pin->port, pin->pin, pin->flags);
     72	}
     73
     74	cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
     75
     76	/* Set FEC1 and FEC2 to MII mode */
     77	clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
     78}
     79
     80static void __init adder875_setup(void)
     81{
     82	cpm_reset();
     83	init_ioports();
     84}
     85
     86static int __init adder875_probe(void)
     87{
     88	return of_machine_is_compatible("analogue-and-micro,adder875");
     89}
     90
     91static const struct of_device_id of_bus_ids[] __initconst = {
     92	{ .compatible = "simple-bus", },
     93	{},
     94};
     95
     96static int __init declare_of_platform_devices(void)
     97{
     98	of_platform_bus_probe(NULL, of_bus_ids, NULL);
     99	return 0;
    100}
    101machine_device_initcall(adder875, declare_of_platform_devices);
    102
    103define_machine(adder875) {
    104	.name = "Adder MPC875",
    105	.probe = adder875_probe,
    106	.setup_arch = adder875_setup,
    107	.init_IRQ = mpc8xx_pic_init,
    108	.get_irq = mpc8xx_get_irq,
    109	.restart = mpc8xx_restart,
    110	.calibrate_decr = generic_calibrate_decr,
    111	.progress = udbg_progress,
    112};