cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mpc86xads_setup.c (3922B)

      1/*arch/powerpc/platforms/8xx/mpc86xads_setup.c
      2 *
      3 * Platform setup for the Freescale mpc86xads board
      4 *
      5 * Vitaly Bordug <vbordug@ru.mvista.com>
      6 *
      7 * Copyright 2005 MontaVista Software Inc.
      8 *
      9 * Heavily modified by Scott Wood <scottwood@freescale.com>
     10 * Copyright 2007 Freescale Semiconductor, Inc.
     11 *
     12 * This file is licensed under the terms of the GNU General Public License
     13 * version 2. This program is licensed "as is" without any warranty of any
     14 * kind, whether express or implied.
     15 */
     16
     17#include <linux/init.h>
     18#include <linux/of_address.h>
     19#include <linux/of_fdt.h>
     20#include <linux/of_platform.h>
     21
     22#include <asm/io.h>
     23#include <asm/machdep.h>
     24#include <asm/time.h>
     25#include <asm/8xx_immap.h>
     26#include <asm/cpm1.h>
     27#include <asm/fs_pd.h>
     28#include <asm/udbg.h>
     29
     30#include "mpc86xads.h"
     31#include "mpc8xx.h"
     32#include "pic.h"
     33
     34struct cpm_pin {
     35	int port, pin, flags;
     36};
     37
     38static struct cpm_pin mpc866ads_pins[] = {
     39	/* SMC1 */
     40	{CPM_PORTB, 24, CPM_PIN_INPUT}, /* RX */
     41	{CPM_PORTB, 25, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
     42
     43	/* SMC2 */
     44	{CPM_PORTB, 21, CPM_PIN_INPUT}, /* RX */
     45	{CPM_PORTB, 20, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
     46
     47	/* SCC1 */
     48	{CPM_PORTA, 6, CPM_PIN_INPUT}, /* CLK1 */
     49	{CPM_PORTA, 7, CPM_PIN_INPUT}, /* CLK2 */
     50	{CPM_PORTA, 14, CPM_PIN_INPUT}, /* TX */
     51	{CPM_PORTA, 15, CPM_PIN_INPUT}, /* RX */
     52	{CPM_PORTB, 19, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TENA */
     53	{CPM_PORTC, 10, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* RENA */
     54	{CPM_PORTC, 11, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* CLSN */
     55
     56	/* MII */
     57	{CPM_PORTD, 3, CPM_PIN_OUTPUT},
     58	{CPM_PORTD, 4, CPM_PIN_OUTPUT},
     59	{CPM_PORTD, 5, CPM_PIN_OUTPUT},
     60	{CPM_PORTD, 6, CPM_PIN_OUTPUT},
     61	{CPM_PORTD, 7, CPM_PIN_OUTPUT},
     62	{CPM_PORTD, 8, CPM_PIN_OUTPUT},
     63	{CPM_PORTD, 9, CPM_PIN_OUTPUT},
     64	{CPM_PORTD, 10, CPM_PIN_OUTPUT},
     65	{CPM_PORTD, 11, CPM_PIN_OUTPUT},
     66	{CPM_PORTD, 12, CPM_PIN_OUTPUT},
     67	{CPM_PORTD, 13, CPM_PIN_OUTPUT},
     68	{CPM_PORTD, 14, CPM_PIN_OUTPUT},
     69	{CPM_PORTD, 15, CPM_PIN_OUTPUT},
     70
     71	/* I2C */
     72	{CPM_PORTB, 26, CPM_PIN_INPUT | CPM_PIN_OPENDRAIN},
     73	{CPM_PORTB, 27, CPM_PIN_INPUT | CPM_PIN_OPENDRAIN},
     74};
     75
     76static void __init init_ioports(void)
     77{
     78	int i;
     79
     80	for (i = 0; i < ARRAY_SIZE(mpc866ads_pins); i++) {
     81		struct cpm_pin *pin = &mpc866ads_pins[i];
     82		cpm1_set_pin(pin->port, pin->pin, pin->flags);
     83	}
     84
     85	cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
     86	cpm1_clk_setup(CPM_CLK_SMC2, CPM_BRG2, CPM_CLK_RTX);
     87	cpm1_clk_setup(CPM_CLK_SCC1, CPM_CLK1, CPM_CLK_TX);
     88	cpm1_clk_setup(CPM_CLK_SCC1, CPM_CLK2, CPM_CLK_RX);
     89
     90	/* Set FEC1 and FEC2 to MII mode */
     91	clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
     92}
     93
     94static void __init mpc86xads_setup_arch(void)
     95{
     96	struct device_node *np;
     97	u32 __iomem *bcsr_io;
     98
     99	cpm_reset();
    100	init_ioports();
    101
    102	np = of_find_compatible_node(NULL, NULL, "fsl,mpc866ads-bcsr");
    103	if (!np) {
    104		printk(KERN_CRIT "Could not find fsl,mpc866ads-bcsr node\n");
    105		return;
    106	}
    107
    108	bcsr_io = of_iomap(np, 0);
    109	of_node_put(np);
    110
    111	if (bcsr_io == NULL) {
    112		printk(KERN_CRIT "Could not remap BCSR\n");
    113		return;
    114	}
    115
    116	clrbits32(bcsr_io, BCSR1_RS232EN_1 | BCSR1_RS232EN_2 | BCSR1_ETHEN);
    117	iounmap(bcsr_io);
    118}
    119
    120static int __init mpc86xads_probe(void)
    121{
    122	return of_machine_is_compatible("fsl,mpc866ads");
    123}
    124
    125static const struct of_device_id of_bus_ids[] __initconst = {
    126	{ .name = "soc", },
    127	{ .name = "cpm", },
    128	{ .name = "localbus", },
    129	{},
    130};
    131
    132static int __init declare_of_platform_devices(void)
    133{
    134	of_platform_bus_probe(NULL, of_bus_ids, NULL);
    135
    136	return 0;
    137}
    138machine_device_initcall(mpc86x_ads, declare_of_platform_devices);
    139
    140define_machine(mpc86x_ads) {
    141	.name			= "MPC86x ADS",
    142	.probe			= mpc86xads_probe,
    143	.setup_arch		= mpc86xads_setup_arch,
    144	.init_IRQ		= mpc8xx_pic_init,
    145	.get_irq		= mpc8xx_get_irq,
    146	.restart		= mpc8xx_restart,
    147	.calibrate_decr		= mpc8xx_calibrate_decr,
    148	.set_rtc_time		= mpc8xx_set_rtc_time,
    149	.get_rtc_time		= mpc8xx_get_rtc_time,
    150	.progress		= udbg_progress,
    151};