cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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interrupt.h (2950B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2#ifndef ASM_CELL_PIC_H
      3#define ASM_CELL_PIC_H
      4#ifdef __KERNEL__
      5/*
      6 * Mapping of IIC pending bits into per-node interrupt numbers.
      7 *
      8 * Interrupt numbers are in the range 0...0x1ff where the top bit
      9 * (0x100) represent the source node. Only 2 nodes are supported with
     10 * the current code though it's trivial to extend that if necessary using
     11 * higher level bits
     12 *
     13 * The bottom 8 bits are split into 2 type bits and 6 data bits that
     14 * depend on the type:
     15 *
     16 * 00 (0x00 | data) : normal interrupt. data is (class << 4) | source
     17 * 01 (0x40 | data) : IO exception. data is the exception number as
     18 *                    defined by bit numbers in IIC_SR
     19 * 10 (0x80 | data) : IPI. data is the IPI number (obtained from the priority)
     20 *                    and node is always 0 (IPIs are per-cpu, their source is
     21 *                    not relevant)
     22 * 11 (0xc0 | data) : reserved
     23 *
     24 * In addition, interrupt number 0x80000000 is defined as always invalid
     25 * (that is the node field is expected to never extend to move than 23 bits)
     26 *
     27 */
     28
     29enum {
     30	IIC_IRQ_INVALID		= 0x80000000u,
     31	IIC_IRQ_NODE_MASK	= 0x100,
     32	IIC_IRQ_NODE_SHIFT	= 8,
     33	IIC_IRQ_MAX		= 0x1ff,
     34	IIC_IRQ_TYPE_MASK	= 0xc0,
     35	IIC_IRQ_TYPE_NORMAL	= 0x00,
     36	IIC_IRQ_TYPE_IOEXC	= 0x40,
     37	IIC_IRQ_TYPE_IPI	= 0x80,
     38	IIC_IRQ_CLASS_SHIFT	= 4,
     39	IIC_IRQ_CLASS_0		= 0x00,
     40	IIC_IRQ_CLASS_1		= 0x10,
     41	IIC_IRQ_CLASS_2		= 0x20,
     42	IIC_SOURCE_COUNT	= 0x200,
     43
     44	/* Here are defined the various source/dest units. Avoid using those
     45	 * definitions if you can, they are mostly here for reference
     46	 */
     47	IIC_UNIT_SPU_0		= 0x4,
     48	IIC_UNIT_SPU_1		= 0x7,
     49	IIC_UNIT_SPU_2		= 0x3,
     50	IIC_UNIT_SPU_3		= 0x8,
     51	IIC_UNIT_SPU_4		= 0x2,
     52	IIC_UNIT_SPU_5		= 0x9,
     53	IIC_UNIT_SPU_6		= 0x1,
     54	IIC_UNIT_SPU_7		= 0xa,
     55	IIC_UNIT_IOC_0		= 0x0,
     56	IIC_UNIT_IOC_1		= 0xb,
     57	IIC_UNIT_THREAD_0	= 0xe, /* target only */
     58	IIC_UNIT_THREAD_1	= 0xf, /* target only */
     59	IIC_UNIT_IIC		= 0xe, /* source only (IO exceptions) */
     60
     61	/* Base numbers for the external interrupts */
     62	IIC_IRQ_EXT_IOIF0	=
     63		IIC_IRQ_TYPE_NORMAL | IIC_IRQ_CLASS_2 | IIC_UNIT_IOC_0,
     64	IIC_IRQ_EXT_IOIF1	=
     65		IIC_IRQ_TYPE_NORMAL | IIC_IRQ_CLASS_2 | IIC_UNIT_IOC_1,
     66
     67	/* Base numbers for the IIC_ISR interrupts */
     68	IIC_IRQ_IOEX_TMI	= IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 63,
     69	IIC_IRQ_IOEX_PMI	= IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 62,
     70	IIC_IRQ_IOEX_ATI	= IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 61,
     71	IIC_IRQ_IOEX_MATBFI	= IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 60,
     72	IIC_IRQ_IOEX_ELDI	= IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 59,
     73
     74	/* Which bits in IIC_ISR are edge sensitive */
     75	IIC_ISR_EDGE_MASK	= 0x4ul,
     76};
     77
     78extern void iic_init_IRQ(void);
     79extern void iic_message_pass(int cpu, int msg);
     80extern void iic_request_IPIs(void);
     81extern void iic_setup_cpu(void);
     82
     83extern u8 iic_get_target_id(int cpu);
     84
     85extern void spider_init_IRQ(void);
     86
     87extern void iic_set_interrupt_routing(int cpu, int thread, int priority);
     88
     89#endif
     90#endif /* ASM_CELL_PIC_H */