cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

spu_priv1_mmio.c (4087B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * spu hypervisor abstraction for direct hardware access.
      4 *
      5 *  (C) Copyright IBM Deutschland Entwicklung GmbH 2005
      6 *  Copyright 2006 Sony Corp.
      7 */
      8
      9#include <linux/interrupt.h>
     10#include <linux/list.h>
     11#include <linux/ptrace.h>
     12#include <linux/wait.h>
     13#include <linux/mm.h>
     14#include <linux/io.h>
     15#include <linux/mutex.h>
     16#include <linux/device.h>
     17#include <linux/sched.h>
     18
     19#include <asm/spu.h>
     20#include <asm/spu_priv1.h>
     21#include <asm/firmware.h>
     22
     23#include "interrupt.h"
     24#include "spu_priv1_mmio.h"
     25
     26static void int_mask_and(struct spu *spu, int class, u64 mask)
     27{
     28	u64 old_mask;
     29
     30	old_mask = in_be64(&spu->priv1->int_mask_RW[class]);
     31	out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask);
     32}
     33
     34static void int_mask_or(struct spu *spu, int class, u64 mask)
     35{
     36	u64 old_mask;
     37
     38	old_mask = in_be64(&spu->priv1->int_mask_RW[class]);
     39	out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask);
     40}
     41
     42static void int_mask_set(struct spu *spu, int class, u64 mask)
     43{
     44	out_be64(&spu->priv1->int_mask_RW[class], mask);
     45}
     46
     47static u64 int_mask_get(struct spu *spu, int class)
     48{
     49	return in_be64(&spu->priv1->int_mask_RW[class]);
     50}
     51
     52static void int_stat_clear(struct spu *spu, int class, u64 stat)
     53{
     54	out_be64(&spu->priv1->int_stat_RW[class], stat);
     55}
     56
     57static u64 int_stat_get(struct spu *spu, int class)
     58{
     59	return in_be64(&spu->priv1->int_stat_RW[class]);
     60}
     61
     62static void cpu_affinity_set(struct spu *spu, int cpu)
     63{
     64	u64 target;
     65	u64 route;
     66
     67	if (nr_cpus_node(spu->node)) {
     68		const struct cpumask *spumask = cpumask_of_node(spu->node),
     69			*cpumask = cpumask_of_node(cpu_to_node(cpu));
     70
     71		if (!cpumask_intersects(spumask, cpumask))
     72			return;
     73	}
     74
     75	target = iic_get_target_id(cpu);
     76	route = target << 48 | target << 32 | target << 16;
     77	out_be64(&spu->priv1->int_route_RW, route);
     78}
     79
     80static u64 mfc_dar_get(struct spu *spu)
     81{
     82	return in_be64(&spu->priv1->mfc_dar_RW);
     83}
     84
     85static u64 mfc_dsisr_get(struct spu *spu)
     86{
     87	return in_be64(&spu->priv1->mfc_dsisr_RW);
     88}
     89
     90static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
     91{
     92	out_be64(&spu->priv1->mfc_dsisr_RW, dsisr);
     93}
     94
     95static void mfc_sdr_setup(struct spu *spu)
     96{
     97	out_be64(&spu->priv1->mfc_sdr_RW, mfspr(SPRN_SDR1));
     98}
     99
    100static void mfc_sr1_set(struct spu *spu, u64 sr1)
    101{
    102	out_be64(&spu->priv1->mfc_sr1_RW, sr1);
    103}
    104
    105static u64 mfc_sr1_get(struct spu *spu)
    106{
    107	return in_be64(&spu->priv1->mfc_sr1_RW);
    108}
    109
    110static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
    111{
    112	out_be64(&spu->priv1->mfc_tclass_id_RW, tclass_id);
    113}
    114
    115static u64 mfc_tclass_id_get(struct spu *spu)
    116{
    117	return in_be64(&spu->priv1->mfc_tclass_id_RW);
    118}
    119
    120static void tlb_invalidate(struct spu *spu)
    121{
    122	out_be64(&spu->priv1->tlb_invalidate_entry_W, 0ul);
    123}
    124
    125static void resource_allocation_groupID_set(struct spu *spu, u64 id)
    126{
    127	out_be64(&spu->priv1->resource_allocation_groupID_RW, id);
    128}
    129
    130static u64 resource_allocation_groupID_get(struct spu *spu)
    131{
    132	return in_be64(&spu->priv1->resource_allocation_groupID_RW);
    133}
    134
    135static void resource_allocation_enable_set(struct spu *spu, u64 enable)
    136{
    137	out_be64(&spu->priv1->resource_allocation_enable_RW, enable);
    138}
    139
    140static u64 resource_allocation_enable_get(struct spu *spu)
    141{
    142	return in_be64(&spu->priv1->resource_allocation_enable_RW);
    143}
    144
    145const struct spu_priv1_ops spu_priv1_mmio_ops =
    146{
    147	.int_mask_and = int_mask_and,
    148	.int_mask_or = int_mask_or,
    149	.int_mask_set = int_mask_set,
    150	.int_mask_get = int_mask_get,
    151	.int_stat_clear = int_stat_clear,
    152	.int_stat_get = int_stat_get,
    153	.cpu_affinity_set = cpu_affinity_set,
    154	.mfc_dar_get = mfc_dar_get,
    155	.mfc_dsisr_get = mfc_dsisr_get,
    156	.mfc_dsisr_set = mfc_dsisr_set,
    157	.mfc_sdr_setup = mfc_sdr_setup,
    158	.mfc_sr1_set = mfc_sr1_set,
    159	.mfc_sr1_get = mfc_sr1_get,
    160	.mfc_tclass_id_set = mfc_tclass_id_set,
    161	.mfc_tclass_id_get = mfc_tclass_id_get,
    162	.tlb_invalidate = tlb_invalidate,
    163	.resource_allocation_groupID_set = resource_allocation_groupID_set,
    164	.resource_allocation_groupID_get = resource_allocation_groupID_get,
    165	.resource_allocation_enable_set = resource_allocation_enable_set,
    166	.resource_allocation_enable_get = resource_allocation_enable_get,
    167};