cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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Kconfig.erratas (1693B)


      1menu "CPU errata selection"
      2
      3config ERRATA_SIFIVE
      4	bool "SiFive errata"
      5	depends on !XIP_KERNEL
      6	select RISCV_ALTERNATIVE
      7	help
      8	  All SiFive errata Kconfig depend on this Kconfig. Disabling
      9	  this Kconfig will disable all SiFive errata. Please say "Y"
     10	  here if your platform uses SiFive CPU cores.
     11
     12	  Otherwise, please say "N" here to avoid unnecessary overhead.
     13
     14config ERRATA_SIFIVE_CIP_453
     15	bool "Apply SiFive errata CIP-453"
     16	depends on ERRATA_SIFIVE && 64BIT
     17	default y
     18	help
     19	  This will apply the SiFive CIP-453 errata to add sign extension
     20	  to the $badaddr when exception type is instruction page fault
     21	  and instruction access fault.
     22
     23	  If you don't know what to do here, say "Y".
     24
     25config ERRATA_SIFIVE_CIP_1200
     26	bool "Apply SiFive errata CIP-1200"
     27	depends on ERRATA_SIFIVE && 64BIT
     28	default y
     29	help
     30	  This will apply the SiFive CIP-1200 errata to repalce all
     31	  "sfence.vma addr" with "sfence.vma" to ensure that the addr
     32	  has been flushed from TLB.
     33
     34	  If you don't know what to do here, say "Y".
     35
     36config ERRATA_THEAD
     37	bool "T-HEAD errata"
     38	depends on !XIP_KERNEL
     39	select RISCV_ALTERNATIVE
     40	help
     41	  All T-HEAD errata Kconfig depend on this Kconfig. Disabling
     42	  this Kconfig will disable all T-HEAD errata. Please say "Y"
     43	  here if your platform uses T-HEAD CPU cores.
     44
     45	  Otherwise, please say "N" here to avoid unnecessary overhead.
     46
     47config ERRATA_THEAD_PBMT
     48	bool "Apply T-Head memory type errata"
     49	depends on ERRATA_THEAD && 64BIT
     50	select RISCV_ALTERNATIVE_EARLY
     51	default y
     52	help
     53	  This will apply the memory type errata to handle the non-standard
     54	  memory type bits in page-table-entries on T-Head SoCs.
     55
     56	  If you don't know what to do here, say "Y".
     57
     58endmenu