cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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canaan_kd233.dts (3439B)

      1// SPDX-License-Identifier: GPL-2.0+
      2/*
      3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
      4 * Copyright (C) 2020 Western Digital Corporation or its affiliates.
      5 */
      6
      7/dts-v1/;
      8
      9#include "k210.dtsi"
     10
     11#include <dt-bindings/gpio/gpio.h>
     12#include <dt-bindings/input/input.h>
     13
     14/ {
     15	model = "Kendryte KD233";
     16	compatible = "canaan,kendryte-kd233", "canaan,kendryte-k210";
     17
     18	chosen {
     19		bootargs = "earlycon console=ttySIF0";
     20		stdout-path = "serial0:115200n8";
     21	};
     22
     23	gpio-leds {
     24		compatible = "gpio-leds";
     25
     26		led0 {
     27			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
     28		};
     29
     30		led1 {
     31			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
     32		};
     33	};
     34
     35	gpio-keys {
     36		compatible = "gpio-keys";
     37
     38		key0 {
     39			label = "KEY0";
     40			linux,code = <BTN_0>;
     41			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
     42		};
     43	};
     44};
     45
     46&fpioa {
     47	pinctrl-0 = <&jtag_pinctrl>;
     48	pinctrl-names = "default";
     49	status = "okay";
     50
     51	jtag_pinctrl: jtag-pinmux {
     52		pinmux = <K210_FPIOA(0, K210_PCF_JTAG_TCLK)>,
     53			 <K210_FPIOA(1, K210_PCF_JTAG_TDI)>,
     54			 <K210_FPIOA(2, K210_PCF_JTAG_TMS)>,
     55			 <K210_FPIOA(3, K210_PCF_JTAG_TDO)>;
     56	};
     57
     58	uarths_pinctrl: uarths-pinmux {
     59		pinmux = <K210_FPIOA(4, K210_PCF_UARTHS_RX)>,
     60			 <K210_FPIOA(5, K210_PCF_UARTHS_TX)>;
     61	};
     62
     63	spi0_pinctrl: spi0-pinmux {
     64		pinmux = <K210_FPIOA(6, K210_PCF_GPIOHS20)>,  /* cs */
     65			 <K210_FPIOA(7, K210_PCF_SPI0_SCLK)>, /* wr */
     66			 <K210_FPIOA(8, K210_PCF_GPIOHS21)>;  /* dc */
     67	};
     68
     69	dvp_pinctrl: dvp-pinmux {
     70		pinmux = <K210_FPIOA(9, K210_PCF_SCCB_SCLK)>,
     71			 <K210_FPIOA(10, K210_PCF_SCCB_SDA)>,
     72			 <K210_FPIOA(11, K210_PCF_DVP_RST)>,
     73			 <K210_FPIOA(12, K210_PCF_DVP_VSYNC)>,
     74			 <K210_FPIOA(13, K210_PCF_DVP_PWDN)>,
     75			 <K210_FPIOA(14, K210_PCF_DVP_XCLK)>,
     76			 <K210_FPIOA(15, K210_PCF_DVP_PCLK)>,
     77			 <K210_FPIOA(17, K210_PCF_DVP_HSYNC)>;
     78	};
     79
     80	gpiohs_pinctrl: gpiohs-pinmux {
     81		pinmux = <K210_FPIOA(16, K210_PCF_GPIOHS0)>,
     82			 <K210_FPIOA(20, K210_PCF_GPIOHS4)>, /* Rot. dip sw line 8 */
     83			 <K210_FPIOA(21, K210_PCF_GPIOHS5)>, /* Rot. dip sw line 4 */
     84			 <K210_FPIOA(22, K210_PCF_GPIOHS6)>, /* Rot. dip sw line 2 */
     85			 <K210_FPIOA(23, K210_PCF_GPIOHS7)>, /* Rot. dip sw line 1 */
     86			 <K210_FPIOA(24, K210_PCF_GPIOHS8)>,
     87			 <K210_FPIOA(25, K210_PCF_GPIOHS9)>,
     88			 <K210_FPIOA(26, K210_PCF_GPIOHS10)>;
     89	};
     90
     91	spi1_pinctrl: spi1-pinmux {
     92		pinmux = <K210_FPIOA(29, K210_PCF_SPI1_SCLK)>,
     93			 <K210_FPIOA(30, K210_PCF_SPI1_D0)>,
     94			 <K210_FPIOA(31, K210_PCF_SPI1_D1)>,
     95			 <K210_FPIOA(32, K210_PCF_GPIOHS16)>; /* cs */
     96	};
     97
     98	i2s0_pinctrl: i2s0-pinmux {
     99		pinmux = <K210_FPIOA(33, K210_PCF_I2S0_IN_D0)>,
    100			 <K210_FPIOA(34, K210_PCF_I2S0_WS)>,
    101			 <K210_FPIOA(35, K210_PCF_I2S0_SCLK)>;
    102	};
    103};
    104
    105&uarths0 {
    106	pinctrl-0 = <&uarths_pinctrl>;
    107	pinctrl-names = "default";
    108	status = "okay";
    109};
    110
    111&gpio0 {
    112	pinctrl-0 = <&gpiohs_pinctrl>;
    113	pinctrl-names = "default";
    114	status = "okay";
    115};
    116
    117&i2s0 {
    118	#sound-dai-cells = <1>;
    119	pinctrl-0 = <&i2s0_pinctrl>;
    120	pinctrl-names = "default";
    121};
    122
    123&spi0 {
    124	pinctrl-0 = <&spi0_pinctrl>;
    125	pinctrl-names = "default";
    126	num-cs = <1>;
    127	cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
    128
    129	panel@0 {
    130		compatible = "ilitek,ili9341";
    131		reg = <0>;
    132		dc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
    133		spi-max-frequency = <15000000>;
    134		status = "disabled";
    135	};
    136};
    137
    138&spi1 {
    139	pinctrl-0 = <&spi1_pinctrl>;
    140	pinctrl-names = "default";
    141	num-cs = <1>;
    142	cs-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
    143	status = "okay";
    144
    145	slot@0 {
    146		compatible = "mmc-spi-slot";
    147		reg = <0>;
    148		voltage-ranges = <3300 3300>;
    149		spi-max-frequency = <25000000>;
    150		broken-cd;
    151	};
    152};