cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mpfs-polarberry.dts (1497B)

      1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
      2/* Copyright (c) 2020-2022 Microchip Technology Inc */
      3
      4/dts-v1/;
      5
      6#include "mpfs.dtsi"
      7#include "mpfs-polarberry-fabric.dtsi"
      8
      9/* Clock frequency (in Hz) of the rtcclk */
     10#define MTIMER_FREQ	1000000
     11
     12/ {
     13	model = "Sundance PolarBerry";
     14	compatible = "sundance,polarberry", "microchip,mpfs";
     15
     16	aliases {
     17		ethernet0 = &mac1;
     18		serial0 = &mmuart0;
     19	};
     20
     21	chosen {
     22		stdout-path = "serial0:115200n8";
     23	};
     24
     25	cpus {
     26		timebase-frequency = <MTIMER_FREQ>;
     27	};
     28
     29	ddrc_cache_lo: memory@80000000 {
     30		device_type = "memory";
     31		reg = <0x0 0x80000000 0x0 0x2e000000>;
     32	};
     33
     34	ddrc_cache_hi: memory@1000000000 {
     35		device_type = "memory";
     36		reg = <0x10 0x00000000 0x0 0xC0000000>;
     37	};
     38};
     39
     40/*
     41 * phy0 is connected to mac0, but the port itself is on the (optional) carrier
     42 * board.
     43 */
     44&mac0 {
     45	phy-mode = "sgmii";
     46	phy-handle = <&phy0>;
     47	status = "disabled";
     48};
     49
     50&mac1 {
     51	phy-mode = "sgmii";
     52	phy-handle = <&phy1>;
     53	status = "okay";
     54
     55	phy1: ethernet-phy@5 {
     56		reg = <5>;
     57		ti,fifo-depth = <0x01>;
     58	};
     59
     60	phy0: ethernet-phy@4 {
     61		reg = <4>;
     62		ti,fifo-depth = <0x01>;
     63	};
     64};
     65
     66&mbox {
     67	status = "okay";
     68};
     69
     70&mmc {
     71	bus-width = <4>;
     72	disable-wp;
     73	cap-sd-highspeed;
     74	cap-mmc-highspeed;
     75	card-detect-delay = <200>;
     76	mmc-ddr-1_8v;
     77	mmc-hs200-1_8v;
     78	sd-uhs-sdr12;
     79	sd-uhs-sdr25;
     80	sd-uhs-sdr50;
     81	sd-uhs-sdr104;
     82	status = "okay";
     83};
     84
     85&mmuart0 {
     86	status = "okay";
     87};
     88
     89&refclk {
     90	clock-frequency = <125000000>;
     91};
     92
     93&rtc {
     94	status = "okay";
     95};
     96
     97&syscontroller {
     98	status = "okay";
     99};