cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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clint.h (797B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Copyright (C) 2020 Google, Inc
      4 */
      5
      6#ifndef _ASM_RISCV_CLINT_H
      7#define _ASM_RISCV_CLINT_H
      8
      9#include <linux/types.h>
     10#include <asm/mmio.h>
     11
     12#ifdef CONFIG_RISCV_M_MODE
     13/*
     14 * This lives in the CLINT driver, but is accessed directly by timex.h to avoid
     15 * any overhead when accessing the MMIO timer.
     16 *
     17 * The ISA defines mtime as a 64-bit memory-mapped register that increments at
     18 * a constant frequency, but it doesn't define some other constraints we depend
     19 * on (most notably ordering constraints, but also some simpler stuff like the
     20 * memory layout).  Thus, this is called "clint_time_val" instead of something
     21 * like "riscv_mtime", to signify that these non-ISA assumptions must hold.
     22 */
     23extern u64 __iomem *clint_time_val;
     24#endif
     25
     26#endif