csr.h (10862B)
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2015 Regents of the University of California 4 */ 5 6#ifndef _ASM_RISCV_CSR_H 7#define _ASM_RISCV_CSR_H 8 9#include <asm/asm.h> 10#include <linux/const.h> 11 12/* Status register flags */ 13#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ 14#define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */ 15#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ 16#define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */ 17#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ 18#define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ 19#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ 20 21#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ 22#define SR_FS_OFF _AC(0x00000000, UL) 23#define SR_FS_INITIAL _AC(0x00002000, UL) 24#define SR_FS_CLEAN _AC(0x00004000, UL) 25#define SR_FS_DIRTY _AC(0x00006000, UL) 26 27#define SR_XS _AC(0x00018000, UL) /* Extension Status */ 28#define SR_XS_OFF _AC(0x00000000, UL) 29#define SR_XS_INITIAL _AC(0x00008000, UL) 30#define SR_XS_CLEAN _AC(0x00010000, UL) 31#define SR_XS_DIRTY _AC(0x00018000, UL) 32 33#ifndef CONFIG_64BIT 34#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ 35#else 36#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ 37#endif 38 39#ifdef CONFIG_64BIT 40#define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */ 41#define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */ 42#define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */ 43#define SR_UXL_SHIFT 32 44#endif 45 46/* SATP flags */ 47#ifndef CONFIG_64BIT 48#define SATP_PPN _AC(0x003FFFFF, UL) 49#define SATP_MODE_32 _AC(0x80000000, UL) 50#define SATP_ASID_BITS 9 51#define SATP_ASID_SHIFT 22 52#define SATP_ASID_MASK _AC(0x1FF, UL) 53#else 54#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) 55#define SATP_MODE_39 _AC(0x8000000000000000, UL) 56#define SATP_MODE_48 _AC(0x9000000000000000, UL) 57#define SATP_MODE_57 _AC(0xa000000000000000, UL) 58#define SATP_ASID_BITS 16 59#define SATP_ASID_SHIFT 44 60#define SATP_ASID_MASK _AC(0xFFFF, UL) 61#endif 62 63/* Exception cause high bit - is an interrupt if set */ 64#define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) 65 66/* Interrupt causes (minus the high bit) */ 67#define IRQ_S_SOFT 1 68#define IRQ_VS_SOFT 2 69#define IRQ_M_SOFT 3 70#define IRQ_S_TIMER 5 71#define IRQ_VS_TIMER 6 72#define IRQ_M_TIMER 7 73#define IRQ_S_EXT 9 74#define IRQ_VS_EXT 10 75#define IRQ_M_EXT 11 76#define IRQ_PMU_OVF 13 77 78/* Exception causes */ 79#define EXC_INST_MISALIGNED 0 80#define EXC_INST_ACCESS 1 81#define EXC_INST_ILLEGAL 2 82#define EXC_BREAKPOINT 3 83#define EXC_LOAD_ACCESS 5 84#define EXC_STORE_ACCESS 7 85#define EXC_SYSCALL 8 86#define EXC_HYPERVISOR_SYSCALL 9 87#define EXC_SUPERVISOR_SYSCALL 10 88#define EXC_INST_PAGE_FAULT 12 89#define EXC_LOAD_PAGE_FAULT 13 90#define EXC_STORE_PAGE_FAULT 15 91#define EXC_INST_GUEST_PAGE_FAULT 20 92#define EXC_LOAD_GUEST_PAGE_FAULT 21 93#define EXC_VIRTUAL_INST_FAULT 22 94#define EXC_STORE_GUEST_PAGE_FAULT 23 95 96/* PMP configuration */ 97#define PMP_R 0x01 98#define PMP_W 0x02 99#define PMP_X 0x04 100#define PMP_A 0x18 101#define PMP_A_TOR 0x08 102#define PMP_A_NA4 0x10 103#define PMP_A_NAPOT 0x18 104#define PMP_L 0x80 105 106/* HSTATUS flags */ 107#ifdef CONFIG_64BIT 108#define HSTATUS_VSXL _AC(0x300000000, UL) 109#define HSTATUS_VSXL_SHIFT 32 110#endif 111#define HSTATUS_VTSR _AC(0x00400000, UL) 112#define HSTATUS_VTW _AC(0x00200000, UL) 113#define HSTATUS_VTVM _AC(0x00100000, UL) 114#define HSTATUS_VGEIN _AC(0x0003f000, UL) 115#define HSTATUS_VGEIN_SHIFT 12 116#define HSTATUS_HU _AC(0x00000200, UL) 117#define HSTATUS_SPVP _AC(0x00000100, UL) 118#define HSTATUS_SPV _AC(0x00000080, UL) 119#define HSTATUS_GVA _AC(0x00000040, UL) 120#define HSTATUS_VSBE _AC(0x00000020, UL) 121 122/* HGATP flags */ 123#define HGATP_MODE_OFF _AC(0, UL) 124#define HGATP_MODE_SV32X4 _AC(1, UL) 125#define HGATP_MODE_SV39X4 _AC(8, UL) 126#define HGATP_MODE_SV48X4 _AC(9, UL) 127#define HGATP_MODE_SV57X4 _AC(10, UL) 128 129#define HGATP32_MODE_SHIFT 31 130#define HGATP32_VMID_SHIFT 22 131#define HGATP32_VMID_MASK _AC(0x1FC00000, UL) 132#define HGATP32_PPN _AC(0x003FFFFF, UL) 133 134#define HGATP64_MODE_SHIFT 60 135#define HGATP64_VMID_SHIFT 44 136#define HGATP64_VMID_MASK _AC(0x03FFF00000000000, UL) 137#define HGATP64_PPN _AC(0x00000FFFFFFFFFFF, UL) 138 139#define HGATP_PAGE_SHIFT 12 140 141#ifdef CONFIG_64BIT 142#define HGATP_PPN HGATP64_PPN 143#define HGATP_VMID_SHIFT HGATP64_VMID_SHIFT 144#define HGATP_VMID_MASK HGATP64_VMID_MASK 145#define HGATP_MODE_SHIFT HGATP64_MODE_SHIFT 146#else 147#define HGATP_PPN HGATP32_PPN 148#define HGATP_VMID_SHIFT HGATP32_VMID_SHIFT 149#define HGATP_VMID_MASK HGATP32_VMID_MASK 150#define HGATP_MODE_SHIFT HGATP32_MODE_SHIFT 151#endif 152 153/* VSIP & HVIP relation */ 154#define VSIP_TO_HVIP_SHIFT (IRQ_VS_SOFT - IRQ_S_SOFT) 155#define VSIP_VALID_MASK ((_AC(1, UL) << IRQ_S_SOFT) | \ 156 (_AC(1, UL) << IRQ_S_TIMER) | \ 157 (_AC(1, UL) << IRQ_S_EXT)) 158 159/* symbolic CSR names: */ 160#define CSR_CYCLE 0xc00 161#define CSR_TIME 0xc01 162#define CSR_INSTRET 0xc02 163#define CSR_HPMCOUNTER3 0xc03 164#define CSR_HPMCOUNTER4 0xc04 165#define CSR_HPMCOUNTER5 0xc05 166#define CSR_HPMCOUNTER6 0xc06 167#define CSR_HPMCOUNTER7 0xc07 168#define CSR_HPMCOUNTER8 0xc08 169#define CSR_HPMCOUNTER9 0xc09 170#define CSR_HPMCOUNTER10 0xc0a 171#define CSR_HPMCOUNTER11 0xc0b 172#define CSR_HPMCOUNTER12 0xc0c 173#define CSR_HPMCOUNTER13 0xc0d 174#define CSR_HPMCOUNTER14 0xc0e 175#define CSR_HPMCOUNTER15 0xc0f 176#define CSR_HPMCOUNTER16 0xc10 177#define CSR_HPMCOUNTER17 0xc11 178#define CSR_HPMCOUNTER18 0xc12 179#define CSR_HPMCOUNTER19 0xc13 180#define CSR_HPMCOUNTER20 0xc14 181#define CSR_HPMCOUNTER21 0xc15 182#define CSR_HPMCOUNTER22 0xc16 183#define CSR_HPMCOUNTER23 0xc17 184#define CSR_HPMCOUNTER24 0xc18 185#define CSR_HPMCOUNTER25 0xc19 186#define CSR_HPMCOUNTER26 0xc1a 187#define CSR_HPMCOUNTER27 0xc1b 188#define CSR_HPMCOUNTER28 0xc1c 189#define CSR_HPMCOUNTER29 0xc1d 190#define CSR_HPMCOUNTER30 0xc1e 191#define CSR_HPMCOUNTER31 0xc1f 192#define CSR_CYCLEH 0xc80 193#define CSR_TIMEH 0xc81 194#define CSR_INSTRETH 0xc82 195#define CSR_HPMCOUNTER3H 0xc83 196#define CSR_HPMCOUNTER4H 0xc84 197#define CSR_HPMCOUNTER5H 0xc85 198#define CSR_HPMCOUNTER6H 0xc86 199#define CSR_HPMCOUNTER7H 0xc87 200#define CSR_HPMCOUNTER8H 0xc88 201#define CSR_HPMCOUNTER9H 0xc89 202#define CSR_HPMCOUNTER10H 0xc8a 203#define CSR_HPMCOUNTER11H 0xc8b 204#define CSR_HPMCOUNTER12H 0xc8c 205#define CSR_HPMCOUNTER13H 0xc8d 206#define CSR_HPMCOUNTER14H 0xc8e 207#define CSR_HPMCOUNTER15H 0xc8f 208#define CSR_HPMCOUNTER16H 0xc90 209#define CSR_HPMCOUNTER17H 0xc91 210#define CSR_HPMCOUNTER18H 0xc92 211#define CSR_HPMCOUNTER19H 0xc93 212#define CSR_HPMCOUNTER20H 0xc94 213#define CSR_HPMCOUNTER21H 0xc95 214#define CSR_HPMCOUNTER22H 0xc96 215#define CSR_HPMCOUNTER23H 0xc97 216#define CSR_HPMCOUNTER24H 0xc98 217#define CSR_HPMCOUNTER25H 0xc99 218#define CSR_HPMCOUNTER26H 0xc9a 219#define CSR_HPMCOUNTER27H 0xc9b 220#define CSR_HPMCOUNTER28H 0xc9c 221#define CSR_HPMCOUNTER29H 0xc9d 222#define CSR_HPMCOUNTER30H 0xc9e 223#define CSR_HPMCOUNTER31H 0xc9f 224 225#define CSR_SSCOUNTOVF 0xda0 226 227#define CSR_SSTATUS 0x100 228#define CSR_SIE 0x104 229#define CSR_STVEC 0x105 230#define CSR_SCOUNTEREN 0x106 231#define CSR_SSCRATCH 0x140 232#define CSR_SEPC 0x141 233#define CSR_SCAUSE 0x142 234#define CSR_STVAL 0x143 235#define CSR_SIP 0x144 236#define CSR_SATP 0x180 237 238#define CSR_VSSTATUS 0x200 239#define CSR_VSIE 0x204 240#define CSR_VSTVEC 0x205 241#define CSR_VSSCRATCH 0x240 242#define CSR_VSEPC 0x241 243#define CSR_VSCAUSE 0x242 244#define CSR_VSTVAL 0x243 245#define CSR_VSIP 0x244 246#define CSR_VSATP 0x280 247 248#define CSR_HSTATUS 0x600 249#define CSR_HEDELEG 0x602 250#define CSR_HIDELEG 0x603 251#define CSR_HIE 0x604 252#define CSR_HTIMEDELTA 0x605 253#define CSR_HCOUNTEREN 0x606 254#define CSR_HGEIE 0x607 255#define CSR_HTIMEDELTAH 0x615 256#define CSR_HTVAL 0x643 257#define CSR_HIP 0x644 258#define CSR_HVIP 0x645 259#define CSR_HTINST 0x64a 260#define CSR_HGATP 0x680 261#define CSR_HGEIP 0xe12 262 263#define CSR_MSTATUS 0x300 264#define CSR_MISA 0x301 265#define CSR_MIE 0x304 266#define CSR_MTVEC 0x305 267#define CSR_MSCRATCH 0x340 268#define CSR_MEPC 0x341 269#define CSR_MCAUSE 0x342 270#define CSR_MTVAL 0x343 271#define CSR_MIP 0x344 272#define CSR_PMPCFG0 0x3a0 273#define CSR_PMPADDR0 0x3b0 274#define CSR_MVENDORID 0xf11 275#define CSR_MARCHID 0xf12 276#define CSR_MIMPID 0xf13 277#define CSR_MHARTID 0xf14 278 279#ifdef CONFIG_RISCV_M_MODE 280# define CSR_STATUS CSR_MSTATUS 281# define CSR_IE CSR_MIE 282# define CSR_TVEC CSR_MTVEC 283# define CSR_SCRATCH CSR_MSCRATCH 284# define CSR_EPC CSR_MEPC 285# define CSR_CAUSE CSR_MCAUSE 286# define CSR_TVAL CSR_MTVAL 287# define CSR_IP CSR_MIP 288 289# define SR_IE SR_MIE 290# define SR_PIE SR_MPIE 291# define SR_PP SR_MPP 292 293# define RV_IRQ_SOFT IRQ_M_SOFT 294# define RV_IRQ_TIMER IRQ_M_TIMER 295# define RV_IRQ_EXT IRQ_M_EXT 296#else /* CONFIG_RISCV_M_MODE */ 297# define CSR_STATUS CSR_SSTATUS 298# define CSR_IE CSR_SIE 299# define CSR_TVEC CSR_STVEC 300# define CSR_SCRATCH CSR_SSCRATCH 301# define CSR_EPC CSR_SEPC 302# define CSR_CAUSE CSR_SCAUSE 303# define CSR_TVAL CSR_STVAL 304# define CSR_IP CSR_SIP 305 306# define SR_IE SR_SIE 307# define SR_PIE SR_SPIE 308# define SR_PP SR_SPP 309 310# define RV_IRQ_SOFT IRQ_S_SOFT 311# define RV_IRQ_TIMER IRQ_S_TIMER 312# define RV_IRQ_EXT IRQ_S_EXT 313# define RV_IRQ_PMU IRQ_PMU_OVF 314# define SIP_LCOFIP (_AC(0x1, UL) << IRQ_PMU_OVF) 315 316#endif /* !CONFIG_RISCV_M_MODE */ 317 318/* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */ 319#define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT) 320#define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER) 321#define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT) 322 323#ifndef __ASSEMBLY__ 324 325#define csr_swap(csr, val) \ 326({ \ 327 unsigned long __v = (unsigned long)(val); \ 328 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ 329 : "=r" (__v) : "rK" (__v) \ 330 : "memory"); \ 331 __v; \ 332}) 333 334#define csr_read(csr) \ 335({ \ 336 register unsigned long __v; \ 337 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ 338 : "=r" (__v) : \ 339 : "memory"); \ 340 __v; \ 341}) 342 343#define csr_write(csr, val) \ 344({ \ 345 unsigned long __v = (unsigned long)(val); \ 346 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ 347 : : "rK" (__v) \ 348 : "memory"); \ 349}) 350 351#define csr_read_set(csr, val) \ 352({ \ 353 unsigned long __v = (unsigned long)(val); \ 354 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ 355 : "=r" (__v) : "rK" (__v) \ 356 : "memory"); \ 357 __v; \ 358}) 359 360#define csr_set(csr, val) \ 361({ \ 362 unsigned long __v = (unsigned long)(val); \ 363 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ 364 : : "rK" (__v) \ 365 : "memory"); \ 366}) 367 368#define csr_read_clear(csr, val) \ 369({ \ 370 unsigned long __v = (unsigned long)(val); \ 371 __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ 372 : "=r" (__v) : "rK" (__v) \ 373 : "memory"); \ 374 __v; \ 375}) 376 377#define csr_clear(csr, val) \ 378({ \ 379 unsigned long __v = (unsigned long)(val); \ 380 __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ 381 : : "rK" (__v) \ 382 : "memory"); \ 383}) 384 385#endif /* __ASSEMBLY__ */ 386 387#endif /* _ASM_RISCV_CSR_H */