cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sbi.h (8519B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Copyright (C) 2015 Regents of the University of California
      4 * Copyright (c) 2020 Western Digital Corporation or its affiliates.
      5 */
      6
      7#ifndef _ASM_RISCV_SBI_H
      8#define _ASM_RISCV_SBI_H
      9
     10#include <linux/types.h>
     11#include <linux/cpumask.h>
     12
     13#ifdef CONFIG_RISCV_SBI
     14enum sbi_ext_id {
     15#ifdef CONFIG_RISCV_SBI_V01
     16	SBI_EXT_0_1_SET_TIMER = 0x0,
     17	SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
     18	SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
     19	SBI_EXT_0_1_CLEAR_IPI = 0x3,
     20	SBI_EXT_0_1_SEND_IPI = 0x4,
     21	SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
     22	SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
     23	SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
     24	SBI_EXT_0_1_SHUTDOWN = 0x8,
     25#endif
     26	SBI_EXT_BASE = 0x10,
     27	SBI_EXT_TIME = 0x54494D45,
     28	SBI_EXT_IPI = 0x735049,
     29	SBI_EXT_RFENCE = 0x52464E43,
     30	SBI_EXT_HSM = 0x48534D,
     31	SBI_EXT_SRST = 0x53525354,
     32	SBI_EXT_PMU = 0x504D55,
     33
     34	/* Experimentals extensions must lie within this range */
     35	SBI_EXT_EXPERIMENTAL_START = 0x08000000,
     36	SBI_EXT_EXPERIMENTAL_END = 0x08FFFFFF,
     37
     38	/* Vendor extensions must lie within this range */
     39	SBI_EXT_VENDOR_START = 0x09000000,
     40	SBI_EXT_VENDOR_END = 0x09FFFFFF,
     41};
     42
     43enum sbi_ext_base_fid {
     44	SBI_EXT_BASE_GET_SPEC_VERSION = 0,
     45	SBI_EXT_BASE_GET_IMP_ID,
     46	SBI_EXT_BASE_GET_IMP_VERSION,
     47	SBI_EXT_BASE_PROBE_EXT,
     48	SBI_EXT_BASE_GET_MVENDORID,
     49	SBI_EXT_BASE_GET_MARCHID,
     50	SBI_EXT_BASE_GET_MIMPID,
     51};
     52
     53enum sbi_ext_time_fid {
     54	SBI_EXT_TIME_SET_TIMER = 0,
     55};
     56
     57enum sbi_ext_ipi_fid {
     58	SBI_EXT_IPI_SEND_IPI = 0,
     59};
     60
     61enum sbi_ext_rfence_fid {
     62	SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
     63	SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
     64	SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
     65	SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID,
     66	SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA,
     67	SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID,
     68	SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA,
     69};
     70
     71enum sbi_ext_hsm_fid {
     72	SBI_EXT_HSM_HART_START = 0,
     73	SBI_EXT_HSM_HART_STOP,
     74	SBI_EXT_HSM_HART_STATUS,
     75	SBI_EXT_HSM_HART_SUSPEND,
     76};
     77
     78enum sbi_hsm_hart_state {
     79	SBI_HSM_STATE_STARTED = 0,
     80	SBI_HSM_STATE_STOPPED,
     81	SBI_HSM_STATE_START_PENDING,
     82	SBI_HSM_STATE_STOP_PENDING,
     83	SBI_HSM_STATE_SUSPENDED,
     84	SBI_HSM_STATE_SUSPEND_PENDING,
     85	SBI_HSM_STATE_RESUME_PENDING,
     86};
     87
     88#define SBI_HSM_SUSP_BASE_MASK			0x7fffffff
     89#define SBI_HSM_SUSP_NON_RET_BIT		0x80000000
     90#define SBI_HSM_SUSP_PLAT_BASE			0x10000000
     91
     92#define SBI_HSM_SUSPEND_RET_DEFAULT		0x00000000
     93#define SBI_HSM_SUSPEND_RET_PLATFORM		SBI_HSM_SUSP_PLAT_BASE
     94#define SBI_HSM_SUSPEND_RET_LAST		SBI_HSM_SUSP_BASE_MASK
     95#define SBI_HSM_SUSPEND_NON_RET_DEFAULT		SBI_HSM_SUSP_NON_RET_BIT
     96#define SBI_HSM_SUSPEND_NON_RET_PLATFORM	(SBI_HSM_SUSP_NON_RET_BIT | \
     97						 SBI_HSM_SUSP_PLAT_BASE)
     98#define SBI_HSM_SUSPEND_NON_RET_LAST		(SBI_HSM_SUSP_NON_RET_BIT | \
     99						 SBI_HSM_SUSP_BASE_MASK)
    100
    101enum sbi_ext_srst_fid {
    102	SBI_EXT_SRST_RESET = 0,
    103};
    104
    105enum sbi_srst_reset_type {
    106	SBI_SRST_RESET_TYPE_SHUTDOWN = 0,
    107	SBI_SRST_RESET_TYPE_COLD_REBOOT,
    108	SBI_SRST_RESET_TYPE_WARM_REBOOT,
    109};
    110
    111enum sbi_srst_reset_reason {
    112	SBI_SRST_RESET_REASON_NONE = 0,
    113	SBI_SRST_RESET_REASON_SYS_FAILURE,
    114};
    115
    116enum sbi_ext_pmu_fid {
    117	SBI_EXT_PMU_NUM_COUNTERS = 0,
    118	SBI_EXT_PMU_COUNTER_GET_INFO,
    119	SBI_EXT_PMU_COUNTER_CFG_MATCH,
    120	SBI_EXT_PMU_COUNTER_START,
    121	SBI_EXT_PMU_COUNTER_STOP,
    122	SBI_EXT_PMU_COUNTER_FW_READ,
    123};
    124
    125#define RISCV_PMU_RAW_EVENT_MASK GENMASK_ULL(55, 0)
    126#define RISCV_PMU_RAW_EVENT_IDX 0x20000
    127
    128/** General pmu event codes specified in SBI PMU extension */
    129enum sbi_pmu_hw_generic_events_t {
    130	SBI_PMU_HW_NO_EVENT			= 0,
    131	SBI_PMU_HW_CPU_CYCLES			= 1,
    132	SBI_PMU_HW_INSTRUCTIONS			= 2,
    133	SBI_PMU_HW_CACHE_REFERENCES		= 3,
    134	SBI_PMU_HW_CACHE_MISSES			= 4,
    135	SBI_PMU_HW_BRANCH_INSTRUCTIONS		= 5,
    136	SBI_PMU_HW_BRANCH_MISSES		= 6,
    137	SBI_PMU_HW_BUS_CYCLES			= 7,
    138	SBI_PMU_HW_STALLED_CYCLES_FRONTEND	= 8,
    139	SBI_PMU_HW_STALLED_CYCLES_BACKEND	= 9,
    140	SBI_PMU_HW_REF_CPU_CYCLES		= 10,
    141
    142	SBI_PMU_HW_GENERAL_MAX,
    143};
    144
    145/**
    146 * Special "firmware" events provided by the firmware, even if the hardware
    147 * does not support performance events. These events are encoded as a raw
    148 * event type in Linux kernel perf framework.
    149 */
    150enum sbi_pmu_fw_generic_events_t {
    151	SBI_PMU_FW_MISALIGNED_LOAD	= 0,
    152	SBI_PMU_FW_MISALIGNED_STORE	= 1,
    153	SBI_PMU_FW_ACCESS_LOAD		= 2,
    154	SBI_PMU_FW_ACCESS_STORE		= 3,
    155	SBI_PMU_FW_ILLEGAL_INSN		= 4,
    156	SBI_PMU_FW_SET_TIMER		= 5,
    157	SBI_PMU_FW_IPI_SENT		= 6,
    158	SBI_PMU_FW_IPI_RECVD		= 7,
    159	SBI_PMU_FW_FENCE_I_SENT		= 8,
    160	SBI_PMU_FW_FENCE_I_RECVD	= 9,
    161	SBI_PMU_FW_SFENCE_VMA_SENT	= 10,
    162	SBI_PMU_FW_SFENCE_VMA_RCVD	= 11,
    163	SBI_PMU_FW_SFENCE_VMA_ASID_SENT	= 12,
    164	SBI_PMU_FW_SFENCE_VMA_ASID_RCVD	= 13,
    165
    166	SBI_PMU_FW_HFENCE_GVMA_SENT	= 14,
    167	SBI_PMU_FW_HFENCE_GVMA_RCVD	= 15,
    168	SBI_PMU_FW_HFENCE_GVMA_VMID_SENT = 16,
    169	SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD = 17,
    170
    171	SBI_PMU_FW_HFENCE_VVMA_SENT	= 18,
    172	SBI_PMU_FW_HFENCE_VVMA_RCVD	= 19,
    173	SBI_PMU_FW_HFENCE_VVMA_ASID_SENT = 20,
    174	SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD = 21,
    175	SBI_PMU_FW_MAX,
    176};
    177
    178/* SBI PMU event types */
    179enum sbi_pmu_event_type {
    180	SBI_PMU_EVENT_TYPE_HW = 0x0,
    181	SBI_PMU_EVENT_TYPE_CACHE = 0x1,
    182	SBI_PMU_EVENT_TYPE_RAW = 0x2,
    183	SBI_PMU_EVENT_TYPE_FW = 0xf,
    184};
    185
    186/* SBI PMU event types */
    187enum sbi_pmu_ctr_type {
    188	SBI_PMU_CTR_TYPE_HW = 0x0,
    189	SBI_PMU_CTR_TYPE_FW,
    190};
    191
    192/* Flags defined for config matching function */
    193#define SBI_PMU_CFG_FLAG_SKIP_MATCH	(1 << 0)
    194#define SBI_PMU_CFG_FLAG_CLEAR_VALUE	(1 << 1)
    195#define SBI_PMU_CFG_FLAG_AUTO_START	(1 << 2)
    196#define SBI_PMU_CFG_FLAG_SET_VUINH	(1 << 3)
    197#define SBI_PMU_CFG_FLAG_SET_VSNH	(1 << 4)
    198#define SBI_PMU_CFG_FLAG_SET_UINH	(1 << 5)
    199#define SBI_PMU_CFG_FLAG_SET_SINH	(1 << 6)
    200#define SBI_PMU_CFG_FLAG_SET_MINH	(1 << 7)
    201
    202/* Flags defined for counter start function */
    203#define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0)
    204
    205/* Flags defined for counter stop function */
    206#define SBI_PMU_STOP_FLAG_RESET (1 << 0)
    207
    208#define SBI_SPEC_VERSION_DEFAULT	0x1
    209#define SBI_SPEC_VERSION_MAJOR_SHIFT	24
    210#define SBI_SPEC_VERSION_MAJOR_MASK	0x7f
    211#define SBI_SPEC_VERSION_MINOR_MASK	0xffffff
    212
    213/* SBI return error codes */
    214#define SBI_SUCCESS		0
    215#define SBI_ERR_FAILURE		-1
    216#define SBI_ERR_NOT_SUPPORTED	-2
    217#define SBI_ERR_INVALID_PARAM	-3
    218#define SBI_ERR_DENIED		-4
    219#define SBI_ERR_INVALID_ADDRESS	-5
    220#define SBI_ERR_ALREADY_AVAILABLE -6
    221#define SBI_ERR_ALREADY_STARTED -7
    222#define SBI_ERR_ALREADY_STOPPED -8
    223
    224extern unsigned long sbi_spec_version;
    225struct sbiret {
    226	long error;
    227	long value;
    228};
    229
    230void sbi_init(void);
    231struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
    232			unsigned long arg1, unsigned long arg2,
    233			unsigned long arg3, unsigned long arg4,
    234			unsigned long arg5);
    235
    236void sbi_console_putchar(int ch);
    237int sbi_console_getchar(void);
    238long sbi_get_mvendorid(void);
    239long sbi_get_marchid(void);
    240long sbi_get_mimpid(void);
    241void sbi_set_timer(uint64_t stime_value);
    242void sbi_shutdown(void);
    243void sbi_clear_ipi(void);
    244int sbi_send_ipi(const struct cpumask *cpu_mask);
    245int sbi_remote_fence_i(const struct cpumask *cpu_mask);
    246int sbi_remote_sfence_vma(const struct cpumask *cpu_mask,
    247			   unsigned long start,
    248			   unsigned long size);
    249
    250int sbi_remote_sfence_vma_asid(const struct cpumask *cpu_mask,
    251				unsigned long start,
    252				unsigned long size,
    253				unsigned long asid);
    254int sbi_remote_hfence_gvma(const struct cpumask *cpu_mask,
    255			   unsigned long start,
    256			   unsigned long size);
    257int sbi_remote_hfence_gvma_vmid(const struct cpumask *cpu_mask,
    258				unsigned long start,
    259				unsigned long size,
    260				unsigned long vmid);
    261int sbi_remote_hfence_vvma(const struct cpumask *cpu_mask,
    262			   unsigned long start,
    263			   unsigned long size);
    264int sbi_remote_hfence_vvma_asid(const struct cpumask *cpu_mask,
    265				unsigned long start,
    266				unsigned long size,
    267				unsigned long asid);
    268int sbi_probe_extension(int ext);
    269
    270/* Check if current SBI specification version is 0.1 or not */
    271static inline int sbi_spec_is_0_1(void)
    272{
    273	return (sbi_spec_version == SBI_SPEC_VERSION_DEFAULT) ? 1 : 0;
    274}
    275
    276/* Get the major version of SBI */
    277static inline unsigned long sbi_major_version(void)
    278{
    279	return (sbi_spec_version >> SBI_SPEC_VERSION_MAJOR_SHIFT) &
    280		SBI_SPEC_VERSION_MAJOR_MASK;
    281}
    282
    283/* Get the minor version of SBI */
    284static inline unsigned long sbi_minor_version(void)
    285{
    286	return sbi_spec_version & SBI_SPEC_VERSION_MINOR_MASK;
    287}
    288
    289/* Make SBI version */
    290static inline unsigned long sbi_mk_version(unsigned long major,
    291					    unsigned long minor)
    292{
    293	return ((major & SBI_SPEC_VERSION_MAJOR_MASK) <<
    294		SBI_SPEC_VERSION_MAJOR_SHIFT) | minor;
    295}
    296
    297int sbi_err_map_linux_errno(int err);
    298#else /* CONFIG_RISCV_SBI */
    299static inline int sbi_remote_fence_i(const struct cpumask *cpu_mask) { return -1; }
    300static inline void sbi_init(void) {}
    301#endif /* CONFIG_RISCV_SBI */
    302#endif /* _ASM_RISCV_SBI_H */