cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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crash_save_regs.S (1599B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * Copyright (C) 2020 FORTH-ICS/CARV
      4 *  Nick Kossifidis <mick@ics.forth.gr>
      5 */
      6
      7#include <asm/asm.h>    	/* For RISCV_* and REG_* macros */
      8#include <asm/csr.h>		/* For CSR_* macros */
      9#include <asm/asm-offsets.h>	/* For offsets on pt_regs */
     10#include <linux/linkage.h>	/* For SYM_* macros */
     11
     12.section ".text"
     13SYM_CODE_START(riscv_crash_save_regs)
     14	REG_S ra,  PT_RA(a0)	/* x1 */
     15	REG_S sp,  PT_SP(a0)	/* x2 */
     16	REG_S gp,  PT_GP(a0)	/* x3 */
     17	REG_S tp,  PT_TP(a0)	/* x4 */
     18	REG_S t0,  PT_T0(a0)	/* x5 */
     19	REG_S t1,  PT_T1(a0)	/* x6 */
     20	REG_S t2,  PT_T2(a0)	/* x7 */
     21	REG_S s0,  PT_S0(a0)	/* x8/fp */
     22	REG_S s1,  PT_S1(a0)	/* x9 */
     23	REG_S a0,  PT_A0(a0)	/* x10 */
     24	REG_S a1,  PT_A1(a0)	/* x11 */
     25	REG_S a2,  PT_A2(a0)	/* x12 */
     26	REG_S a3,  PT_A3(a0)	/* x13 */
     27	REG_S a4,  PT_A4(a0)	/* x14 */
     28	REG_S a5,  PT_A5(a0)	/* x15 */
     29	REG_S a6,  PT_A6(a0)	/* x16 */
     30	REG_S a7,  PT_A7(a0)	/* x17 */
     31	REG_S s2,  PT_S2(a0)	/* x18 */
     32	REG_S s3,  PT_S3(a0)	/* x19 */
     33	REG_S s4,  PT_S4(a0)	/* x20 */
     34	REG_S s5,  PT_S5(a0)	/* x21 */
     35	REG_S s6,  PT_S6(a0)	/* x22 */
     36	REG_S s7,  PT_S7(a0)	/* x23 */
     37	REG_S s8,  PT_S8(a0)	/* x24 */
     38	REG_S s9,  PT_S9(a0)	/* x25 */
     39	REG_S s10, PT_S10(a0)	/* x26 */
     40	REG_S s11, PT_S11(a0)	/* x27 */
     41	REG_S t3,  PT_T3(a0)	/* x28 */
     42	REG_S t4,  PT_T4(a0)	/* x29 */
     43	REG_S t5,  PT_T5(a0)	/* x30 */
     44	REG_S t6,  PT_T6(a0)	/* x31 */
     45
     46	csrr t1, CSR_STATUS
     47	csrr t2, CSR_EPC
     48	csrr t3, CSR_TVAL
     49	csrr t4, CSR_CAUSE
     50
     51	REG_S t1, PT_STATUS(a0)
     52	REG_S t2, PT_EPC(a0)
     53	REG_S t3, PT_BADADDR(a0)
     54	REG_S t4, PT_CAUSE(a0)
     55	ret
     56SYM_CODE_END(riscv_crash_save_regs)