ipl_data.c (3926B)
1// SPDX-License-Identifier: GPL-2.0 2 3#include <linux/compat.h> 4#include <linux/ptrace.h> 5#include <asm/cio.h> 6#include <asm/asm-offsets.h> 7#include "boot.h" 8 9#define CCW0(cmd, addr, cnt, flg) \ 10 { .cmd_code = cmd, .cda = addr, .count = cnt, .flags = flg, } 11 12#define PSW_MASK_DISABLED (PSW_MASK_WAIT | PSW_MASK_EA | PSW_MASK_BA) 13 14struct ipl_lowcore { 15 psw_t32 ipl_psw; /* 0x0000 */ 16 struct ccw0 ccwpgm[2]; /* 0x0008 */ 17 u8 fill[56]; /* 0x0018 */ 18 struct ccw0 ccwpgmcc[20]; /* 0x0050 */ 19 u8 pad_0xf0[0x01a0-0x00f0]; /* 0x00f0 */ 20 psw_t restart_psw; /* 0x01a0 */ 21 psw_t external_new_psw; /* 0x01b0 */ 22 psw_t svc_new_psw; /* 0x01c0 */ 23 psw_t program_new_psw; /* 0x01d0 */ 24 psw_t mcck_new_psw; /* 0x01e0 */ 25 psw_t io_new_psw; /* 0x01f0 */ 26}; 27 28/* 29 * Initial lowcore for IPL: the first 24 bytes are loaded by IPL to 30 * addresses 0-23 (a PSW and two CCWs). Bytes 24-79 are discarded. 31 * The next 160 bytes are loaded to addresses 0x18-0xb7. They form 32 * the continuation of the CCW program started by IPL and load the 33 * range 0x0f0-0x730 from the image to the range 0x0f0-0x730 in 34 * memory. At the end of the channel program the PSW at location 0 is 35 * loaded. 36 * Initial processing starts at 0x200 = iplstart. 37 * 38 * The restart psw points to iplstart which allows to load a kernel 39 * image into memory and starting it by a psw restart on any cpu. All 40 * other default psw new locations contain a disabled wait psw where 41 * the address indicates which psw was loaded. 42 * 43 * Note that the 'file' utility can detect s390 kernel images. For 44 * that to succeed the two initial CCWs, and the 0x40 fill bytes must 45 * be present. 46 */ 47static struct ipl_lowcore ipl_lowcore __used __section(".ipldata") = { 48 .ipl_psw = { .mask = PSW32_MASK_BASE, .addr = PSW32_ADDR_AMODE | IPL_START }, 49 .ccwpgm = { 50 [ 0] = CCW0(CCW_CMD_READ_IPL, 0x018, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 51 [ 1] = CCW0(CCW_CMD_READ_IPL, 0x068, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 52 }, 53 .fill = { 54 [ 0 ... 55] = 0x40, 55 }, 56 .ccwpgmcc = { 57 [ 0] = CCW0(CCW_CMD_READ_IPL, 0x0f0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 58 [ 1] = CCW0(CCW_CMD_READ_IPL, 0x140, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 59 [ 2] = CCW0(CCW_CMD_READ_IPL, 0x190, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 60 [ 3] = CCW0(CCW_CMD_READ_IPL, 0x1e0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 61 [ 4] = CCW0(CCW_CMD_READ_IPL, 0x230, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 62 [ 5] = CCW0(CCW_CMD_READ_IPL, 0x280, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 63 [ 6] = CCW0(CCW_CMD_READ_IPL, 0x2d0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 64 [ 7] = CCW0(CCW_CMD_READ_IPL, 0x320, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 65 [ 8] = CCW0(CCW_CMD_READ_IPL, 0x370, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 66 [ 9] = CCW0(CCW_CMD_READ_IPL, 0x3c0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 67 [10] = CCW0(CCW_CMD_READ_IPL, 0x410, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 68 [11] = CCW0(CCW_CMD_READ_IPL, 0x460, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 69 [12] = CCW0(CCW_CMD_READ_IPL, 0x4b0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 70 [13] = CCW0(CCW_CMD_READ_IPL, 0x500, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 71 [14] = CCW0(CCW_CMD_READ_IPL, 0x550, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 72 [15] = CCW0(CCW_CMD_READ_IPL, 0x5a0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 73 [16] = CCW0(CCW_CMD_READ_IPL, 0x5f0, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 74 [17] = CCW0(CCW_CMD_READ_IPL, 0x640, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 75 [18] = CCW0(CCW_CMD_READ_IPL, 0x690, 0x50, CCW_FLAG_SLI | CCW_FLAG_CC), 76 [19] = CCW0(CCW_CMD_READ_IPL, 0x6e0, 0x50, CCW_FLAG_SLI), 77 }, 78 .restart_psw = { .mask = 0, .addr = IPL_START, }, 79 .external_new_psw = { .mask = PSW_MASK_DISABLED, .addr = __LC_EXT_NEW_PSW, }, 80 .svc_new_psw = { .mask = PSW_MASK_DISABLED, .addr = __LC_SVC_NEW_PSW, }, 81 .program_new_psw = { .mask = PSW_MASK_DISABLED, .addr = __LC_PGM_NEW_PSW, }, 82 .mcck_new_psw = { .mask = PSW_MASK_DISABLED, .addr = __LC_MCK_NEW_PSW, }, 83 .io_new_psw = { .mask = PSW_MASK_DISABLED, .addr = __LC_IO_NEW_PSW, }, 84};