cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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uaccess.c (4638B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 *  Standard user space access functions based on mvcp/mvcs and doing
      4 *  interesting things in the secondary space mode.
      5 *
      6 *    Copyright IBM Corp. 2006,2014
      7 *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
      8 *		 Gerald Schaefer (gerald.schaefer@de.ibm.com)
      9 */
     10
     11#include <linux/uaccess.h>
     12#include <linux/export.h>
     13#include <linux/mm.h>
     14#include <asm/asm-extable.h>
     15
     16#ifdef CONFIG_DEBUG_ENTRY
     17void debug_user_asce(int exit)
     18{
     19	unsigned long cr1, cr7;
     20
     21	__ctl_store(cr1, 1, 1);
     22	__ctl_store(cr7, 7, 7);
     23	if (cr1 == S390_lowcore.kernel_asce && cr7 == S390_lowcore.user_asce)
     24		return;
     25	panic("incorrect ASCE on kernel %s\n"
     26	      "cr1:    %016lx cr7:  %016lx\n"
     27	      "kernel: %016llx user: %016llx\n",
     28	      exit ? "exit" : "entry", cr1, cr7,
     29	      S390_lowcore.kernel_asce, S390_lowcore.user_asce);
     30
     31}
     32#endif /*CONFIG_DEBUG_ENTRY */
     33
     34static unsigned long raw_copy_from_user_key(void *to, const void __user *from,
     35					    unsigned long size, unsigned long key)
     36{
     37	unsigned long tmp1, tmp2;
     38	union oac spec = {
     39		.oac2.key = key,
     40		.oac2.as = PSW_BITS_AS_SECONDARY,
     41		.oac2.k = 1,
     42		.oac2.a = 1,
     43	};
     44
     45	tmp1 = -4096UL;
     46	asm volatile(
     47		"   lr	  0,%[spec]\n"
     48		"0: mvcos 0(%2),0(%1),%0\n"
     49		"6: jz    4f\n"
     50		"1: algr  %0,%3\n"
     51		"   slgr  %1,%3\n"
     52		"   slgr  %2,%3\n"
     53		"   j     0b\n"
     54		"2: la    %4,4095(%1)\n"/* %4 = ptr + 4095 */
     55		"   nr    %4,%3\n"	/* %4 = (ptr + 4095) & -4096 */
     56		"   slgr  %4,%1\n"
     57		"   clgr  %0,%4\n"	/* copy crosses next page boundary? */
     58		"   jnh   5f\n"
     59		"3: mvcos 0(%2),0(%1),%4\n"
     60		"7: slgr  %0,%4\n"
     61		"   j     5f\n"
     62		"4: slgr  %0,%0\n"
     63		"5:\n"
     64		EX_TABLE(0b,2b) EX_TABLE(3b,5b) EX_TABLE(6b,2b) EX_TABLE(7b,5b)
     65		: "+a" (size), "+a" (from), "+a" (to), "+a" (tmp1), "=a" (tmp2)
     66		: [spec] "d" (spec.val)
     67		: "cc", "memory", "0");
     68	return size;
     69}
     70
     71unsigned long raw_copy_from_user(void *to, const void __user *from, unsigned long n)
     72{
     73	return raw_copy_from_user_key(to, from, n, 0);
     74}
     75EXPORT_SYMBOL(raw_copy_from_user);
     76
     77unsigned long _copy_from_user_key(void *to, const void __user *from,
     78				  unsigned long n, unsigned long key)
     79{
     80	unsigned long res = n;
     81
     82	might_fault();
     83	if (!should_fail_usercopy()) {
     84		instrument_copy_from_user(to, from, n);
     85		res = raw_copy_from_user_key(to, from, n, key);
     86	}
     87	if (unlikely(res))
     88		memset(to + (n - res), 0, res);
     89	return res;
     90}
     91EXPORT_SYMBOL(_copy_from_user_key);
     92
     93static unsigned long raw_copy_to_user_key(void __user *to, const void *from,
     94					  unsigned long size, unsigned long key)
     95{
     96	unsigned long tmp1, tmp2;
     97	union oac spec = {
     98		.oac1.key = key,
     99		.oac1.as = PSW_BITS_AS_SECONDARY,
    100		.oac1.k = 1,
    101		.oac1.a = 1,
    102	};
    103
    104	tmp1 = -4096UL;
    105	asm volatile(
    106		"   lr	  0,%[spec]\n"
    107		"0: mvcos 0(%1),0(%2),%0\n"
    108		"6: jz    4f\n"
    109		"1: algr  %0,%3\n"
    110		"   slgr  %1,%3\n"
    111		"   slgr  %2,%3\n"
    112		"   j     0b\n"
    113		"2: la    %4,4095(%1)\n"/* %4 = ptr + 4095 */
    114		"   nr    %4,%3\n"	/* %4 = (ptr + 4095) & -4096 */
    115		"   slgr  %4,%1\n"
    116		"   clgr  %0,%4\n"	/* copy crosses next page boundary? */
    117		"   jnh   5f\n"
    118		"3: mvcos 0(%1),0(%2),%4\n"
    119		"7: slgr  %0,%4\n"
    120		"   j     5f\n"
    121		"4: slgr  %0,%0\n"
    122		"5:\n"
    123		EX_TABLE(0b,2b) EX_TABLE(3b,5b) EX_TABLE(6b,2b) EX_TABLE(7b,5b)
    124		: "+a" (size), "+a" (to), "+a" (from), "+a" (tmp1), "=a" (tmp2)
    125		: [spec] "d" (spec.val)
    126		: "cc", "memory", "0");
    127	return size;
    128}
    129
    130unsigned long raw_copy_to_user(void __user *to, const void *from, unsigned long n)
    131{
    132	return raw_copy_to_user_key(to, from, n, 0);
    133}
    134EXPORT_SYMBOL(raw_copy_to_user);
    135
    136unsigned long _copy_to_user_key(void __user *to, const void *from,
    137				unsigned long n, unsigned long key)
    138{
    139	might_fault();
    140	if (should_fail_usercopy())
    141		return n;
    142	instrument_copy_to_user(to, from, n);
    143	return raw_copy_to_user_key(to, from, n, key);
    144}
    145EXPORT_SYMBOL(_copy_to_user_key);
    146
    147unsigned long __clear_user(void __user *to, unsigned long size)
    148{
    149	unsigned long tmp1, tmp2;
    150	union oac spec = {
    151		.oac1.as = PSW_BITS_AS_SECONDARY,
    152		.oac1.a = 1,
    153	};
    154
    155	tmp1 = -4096UL;
    156	asm volatile(
    157		"   lr	  0,%[spec]\n"
    158		"0: mvcos 0(%1),0(%4),%0\n"
    159		"   jz	  4f\n"
    160		"1: algr  %0,%2\n"
    161		"   slgr  %1,%2\n"
    162		"   j	  0b\n"
    163		"2: la	  %3,4095(%1)\n"/* %4 = to + 4095 */
    164		"   nr	  %3,%2\n"	/* %4 = (to + 4095) & -4096 */
    165		"   slgr  %3,%1\n"
    166		"   clgr  %0,%3\n"	/* copy crosses next page boundary? */
    167		"   jnh	  5f\n"
    168		"3: mvcos 0(%1),0(%4),%3\n"
    169		"   slgr  %0,%3\n"
    170		"   j	  5f\n"
    171		"4: slgr  %0,%0\n"
    172		"5:\n"
    173		EX_TABLE(0b,2b) EX_TABLE(3b,5b)
    174		: "+a" (size), "+a" (to), "+a" (tmp1), "=a" (tmp2)
    175		: "a" (empty_zero_page), [spec] "d" (spec.val)
    176		: "cc", "memory", "0");
    177	return size;
    178}
    179EXPORT_SYMBOL(__clear_user);