cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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Kconfig.cpu (2373B)


      1# SPDX-License-Identifier: GPL-2.0
      2menu "Processor features"
      3
      4choice
      5	prompt "Endianness selection" 
      6	default CPU_LITTLE_ENDIAN
      7	help
      8	  Some SuperH machines can be configured for either little or big
      9	  endian byte order. These modes require different kernels.
     10
     11config CPU_LITTLE_ENDIAN
     12	bool "Little Endian"
     13
     14config CPU_BIG_ENDIAN
     15	bool "Big Endian"
     16
     17endchoice
     18
     19config SH_FPU
     20	def_bool y
     21	prompt "FPU support"
     22	depends on CPU_HAS_FPU
     23	help
     24	  Selecting this option will enable support for SH processors that
     25	  have FPU units (ie, SH77xx).
     26
     27	  This option must be set in order to enable the FPU.
     28
     29config SH_FPU_EMU
     30	def_bool n
     31	prompt "FPU emulation support"
     32	depends on !SH_FPU
     33	help
     34	  Selecting this option will enable support for software FPU emulation.
     35	  Most SH-3 users will want to say Y here, whereas most SH-4 users will
     36	  want to say N.
     37
     38config SH_DSP
     39	def_bool y
     40	prompt "DSP support"
     41	depends on CPU_HAS_DSP
     42	help
     43	  Selecting this option will enable support for SH processors that
     44	  have DSP units (ie, SH2-DSP, SH3-DSP, and SH4AL-DSP).
     45
     46	  This option must be set in order to enable the DSP.
     47
     48config SH_ADC
     49	def_bool y
     50	prompt "ADC support"
     51	depends on CPU_SH3
     52	help
     53	  Selecting this option will allow the Linux kernel to use SH3 on-chip
     54	  ADC module.
     55
     56	  If unsure, say N.
     57
     58config SH_STORE_QUEUES
     59	bool "Support for Store Queues"
     60	depends on CPU_SH4
     61	help
     62	  Selecting this option will enable an in-kernel API for manipulating
     63	  the store queues integrated in the SH-4 processors.
     64
     65config SPECULATIVE_EXECUTION
     66	bool "Speculative subroutine return"
     67	depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || CPU_SUBTYPE_SH7786
     68	help
     69	  This enables support for a speculative instruction fetch for
     70	  subroutine return. There are various pitfalls associated with
     71	  this, as outlined in the SH7780 hardware manual.
     72
     73	  If unsure, say N.
     74
     75config CPU_HAS_INTEVT
     76	bool
     77
     78config CPU_HAS_IPR_IRQ
     79	bool
     80
     81config CPU_HAS_SR_RB
     82	bool
     83	help
     84	  This will enable the use of SR.RB register bank usage. Processors
     85	  that are lacking this bit must have another method in place for
     86	  accomplishing what is taken care of by the banked registers.
     87
     88	  See <file:Documentation/sh/register-banks.rst> for further
     89	  information on SR.RB and register banking in the kernel in general.
     90
     91config CPU_HAS_PTEAEX
     92	bool
     93
     94config CPU_HAS_DSP
     95	bool
     96
     97config CPU_HAS_FPU
     98	bool
     99
    100endmenu