cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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irq.c (950B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * SDK7786 FPGA IRQ Controller Support.
      4 *
      5 * Copyright (C) 2010  Matt Fleming
      6 * Copyright (C) 2010  Paul Mundt
      7 */
      8#include <linux/irq.h>
      9#include <mach/fpga.h>
     10#include <mach/irq.h>
     11
     12enum {
     13	ATA_IRQ_BIT		= 1,
     14	SPI_BUSY_BIT		= 2,
     15	LIRQ5_BIT		= 3,
     16	LIRQ6_BIT		= 4,
     17	LIRQ7_BIT		= 5,
     18	LIRQ8_BIT		= 6,
     19	KEY_IRQ_BIT		= 7,
     20	PEN_IRQ_BIT		= 8,
     21	ETH_IRQ_BIT		= 9,
     22	RTC_ALARM_BIT		= 10,
     23	CRYSTAL_FAIL_BIT	= 12,
     24	ETH_PME_BIT		= 14,
     25};
     26
     27void __init sdk7786_init_irq(void)
     28{
     29	unsigned int tmp;
     30
     31	/* Enable priority encoding for all IRLs */
     32	fpga_write_reg(fpga_read_reg(INTMSR) | 0x0303, INTMSR);
     33
     34	/* Clear FPGA interrupt status registers */
     35	fpga_write_reg(0x0000, INTASR);
     36	fpga_write_reg(0x0000, INTBSR);
     37
     38	/* Unmask FPGA interrupts */
     39	tmp = fpga_read_reg(INTAMR);
     40	tmp &= ~(1 << ETH_IRQ_BIT);
     41	fpga_write_reg(tmp, INTAMR);
     42
     43	plat_irq_setup_pins(IRQ_MODE_IRL7654_MASK);
     44	plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK);
     45}