cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sram.c (1555B)


      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * SDK7786 FPGA SRAM Support.
      4 *
      5 * Copyright (C) 2010  Paul Mundt
      6 */
      7#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
      8
      9#include <linux/init.h>
     10#include <linux/kernel.h>
     11#include <linux/types.h>
     12#include <linux/io.h>
     13#include <linux/string.h>
     14#include <mach/fpga.h>
     15#include <asm/sram.h>
     16#include <linux/sizes.h>
     17
     18static int __init fpga_sram_init(void)
     19{
     20	unsigned long phys;
     21	unsigned int area;
     22	void __iomem *vaddr;
     23	int ret;
     24	u16 data;
     25
     26	/* Enable FPGA SRAM */
     27	data = fpga_read_reg(LCLASR);
     28	data |= LCLASR_FRAMEN;
     29	fpga_write_reg(data, LCLASR);
     30
     31	/*
     32	 * FPGA_SEL determines the area mapping
     33	 */
     34	area = (data & LCLASR_FPGA_SEL_MASK) >> LCLASR_FPGA_SEL_SHIFT;
     35	if (unlikely(area == LCLASR_AREA_MASK)) {
     36		pr_err("FPGA memory unmapped.\n");
     37		return -ENXIO;
     38	}
     39
     40	/*
     41	 * The memory itself occupies a 2KiB range at the top of the area
     42	 * immediately below the system registers.
     43	 */
     44	phys = (area << 26) + SZ_64M - SZ_4K;
     45
     46	/*
     47	 * The FPGA SRAM resides in translatable physical space, so set
     48	 * up a mapping prior to inserting it in to the pool.
     49	 */
     50	vaddr = ioremap(phys, SZ_2K);
     51	if (unlikely(!vaddr)) {
     52		pr_err("Failed remapping FPGA memory.\n");
     53		return -ENXIO;
     54	}
     55
     56	pr_info("Adding %dKiB of FPGA memory at 0x%08lx-0x%08lx "
     57		"(area %d) to pool.\n",
     58		SZ_2K >> 10, phys, phys + SZ_2K - 1, area);
     59
     60	ret = gen_pool_add(sram_pool, (unsigned long)vaddr, SZ_2K, -1);
     61	if (unlikely(ret < 0)) {
     62		pr_err("Failed adding memory\n");
     63		iounmap(vaddr);
     64		return ret;
     65	}
     66
     67	return 0;
     68}
     69postcore_initcall(fpga_sram_init);