cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fixups-landisk.c (1457B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * arch/sh/drivers/pci/fixups-landisk.c
      4 *
      5 * PCI initialization for the I-O DATA Device, Inc. LANDISK board
      6 *
      7 * Copyright (C) 2006 kogiidena
      8 * Copyright (C) 2010 Nobuhiro Iwamatsu
      9 */
     10#include <linux/kernel.h>
     11#include <linux/types.h>
     12#include <linux/init.h>
     13#include <linux/delay.h>
     14#include <linux/pci.h>
     15#include <linux/sh_intc.h>
     16#include "pci-sh4.h"
     17
     18#define PCIMCR_MRSET_OFF	0xBFFFFFFF
     19#define PCIMCR_RFSH_OFF		0xFFFFFFFB
     20
     21int pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
     22{
     23	/*
     24	 * slot0: pin1-4 = irq5,6,7,8
     25	 * slot1: pin1-4 = irq6,7,8,5
     26	 * slot2: pin1-4 = irq7,8,5,6
     27	 * slot3: pin1-4 = irq8,5,6,7
     28	 */
     29	int irq = ((slot + pin - 1) & 0x3) + evt2irq(0x2a0);
     30
     31	if ((slot | (pin - 1)) > 0x3) {
     32		printk(KERN_WARNING "PCI: Bad IRQ mapping request for slot %d pin %c\n",
     33		       slot, pin - 1 + 'A');
     34		return -1;
     35	}
     36	return irq;
     37}
     38
     39int pci_fixup_pcic(struct pci_channel *chan)
     40{
     41	unsigned long bcr1, mcr;
     42
     43	bcr1 = __raw_readl(SH7751_BCR1);
     44	bcr1 |= 0x40080000;	/* Enable Bit 19 BREQEN, set PCIC to slave */
     45	pci_write_reg(chan, bcr1, SH4_PCIBCR1);
     46
     47	mcr = __raw_readl(SH7751_MCR);
     48	mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
     49	pci_write_reg(chan, mcr, SH4_PCIMCR);
     50
     51	pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5);
     52	pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6);
     53	pci_write_reg(chan, 0x0c000000, SH4_PCILAR0);
     54	pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
     55
     56	return 0;
     57}