cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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magicpanelr2.h (1820B)

      1/* SPDX-License-Identifier: GPL-2.0
      2 *
      3 *  include/asm-sh/magicpanelr2.h
      4 *
      5 *  Copyright (C) 2007  Markus Brunner, Mark Jonas
      6 *
      7 *  I/O addresses and bitmasks for Magic Panel Release 2 board
      8 */
      9
     10#ifndef __ASM_SH_MAGICPANELR2_H
     11#define __ASM_SH_MAGICPANELR2_H
     12
     13#include <linux/gpio.h>
     14
     15#define __IO_PREFIX mpr2
     16#include <asm/io_generic.h>
     17
     18
     19#define SETBITS_OUTB(mask, reg)   __raw_writeb(__raw_readb(reg) | mask, reg)
     20#define SETBITS_OUTW(mask, reg)   __raw_writew(__raw_readw(reg) | mask, reg)
     21#define SETBITS_OUTL(mask, reg)   __raw_writel(__raw_readl(reg) | mask, reg)
     22#define CLRBITS_OUTB(mask, reg)   __raw_writeb(__raw_readb(reg) & ~mask, reg)
     23#define CLRBITS_OUTW(mask, reg)   __raw_writew(__raw_readw(reg) & ~mask, reg)
     24#define CLRBITS_OUTL(mask, reg)   __raw_writel(__raw_readl(reg) & ~mask, reg)
     25
     26
     27#define PA_LED          PORT_PADR      /* LED */
     28
     29
     30/* BSC */
     31#define CMNCR           0xA4FD0000UL
     32#define CS0BCR          0xA4FD0004UL
     33#define CS2BCR          0xA4FD0008UL
     34#define CS3BCR          0xA4FD000CUL
     35#define CS4BCR          0xA4FD0010UL
     36#define CS5ABCR         0xA4FD0014UL
     37#define CS5BBCR         0xA4FD0018UL
     38#define CS6ABCR         0xA4FD001CUL
     39#define CS6BBCR         0xA4FD0020UL
     40#define CS0WCR          0xA4FD0024UL
     41#define CS2WCR          0xA4FD0028UL
     42#define CS3WCR          0xA4FD002CUL
     43#define CS4WCR          0xA4FD0030UL
     44#define CS5AWCR         0xA4FD0034UL
     45#define CS5BWCR         0xA4FD0038UL
     46#define CS6AWCR         0xA4FD003CUL
     47#define CS6BWCR         0xA4FD0040UL
     48
     49
     50/* usb */
     51
     52#define PORT_UTRCTL		0xA405012CUL
     53#define PORT_UCLKCR_W		0xA40A0008UL
     54
     55#define INTC_ICR0		0xA414FEE0UL
     56#define INTC_ICR1		0xA4140010UL
     57#define INTC_ICR2		0xA4140012UL
     58
     59/* MTD */
     60
     61#define MPR2_MTD_BOOTLOADER_SIZE	0x00060000UL
     62#define MPR2_MTD_KERNEL_SIZE		0x00200000UL
     63
     64#endif  /* __ASM_SH_MAGICPANELR2_H */