sh2007.h (3516B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef __MACH_SH2007_H 3#define __MACH_SH2007_H 4 5#define CS5BCR 0xff802050 6#define CS5WCR 0xff802058 7#define CS5PCR 0xff802070 8 9#define BUS_SZ8 1 10#define BUS_SZ16 2 11#define BUS_SZ32 3 12 13#define PCMCIA_IODYN 1 14#define PCMCIA_ATA 0 15#define PCMCIA_IO8 2 16#define PCMCIA_IO16 3 17#define PCMCIA_COMM8 4 18#define PCMCIA_COMM16 5 19#define PCMCIA_ATTR8 6 20#define PCMCIA_ATTR16 7 21 22#define TYPE_SRAM 0 23#define TYPE_PCMCIA 4 24 25/* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */ 26#define IWW5 0 27#define IWW6 3 28/* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */ 29#define IWRWD5 2 30#define IWRWD6 2 31/* same area, read-write delay (0-7:0,1,2,3,4,5,6,7) */ 32#define IWRWS5 2 33#define IWRWS6 2 34/* different area, read-read delay (0-7:0,1,2,3,4,5,6,7) */ 35#define IWRRD5 2 36#define IWRRD6 2 37/* same area, read-read delay (0-7:0,1,2,3,4,5,6,7) */ 38#define IWRRS5 0 39#define IWRRS6 2 40/* burst count (0-3:4,8,16,32) */ 41#define BST5 0 42#define BST6 0 43/* bus size */ 44#define SZ5 BUS_SZ16 45#define SZ6 BUS_SZ16 46/* RD hold for SRAM (0-1:0,1) */ 47#define RDSPL5 0 48#define RDSPL6 0 49/* Burst pitch (0-7:0,1,2,3,4,5,6,7) */ 50#define BW5 0 51#define BW6 0 52/* Multiplex (0-1:0,1) */ 53#define MPX5 0 54#define MPX6 0 55/* device type */ 56#define TYPE5 TYPE_PCMCIA 57#define TYPE6 TYPE_PCMCIA 58/* address setup before assert CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */ 59#define ADS5 0 60#define ADS6 0 61/* address hold after negate CSn for SRAM (0-7:0,1,2,3,4,5,6,7) */ 62#define ADH5 0 63#define ADH6 0 64/* CSn assert to RD assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ 65#define RDS5 0 66#define RDS6 0 67/* RD negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ 68#define RDH5 0 69#define RDH6 0 70/* CSn assert to WE assert delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ 71#define WTS5 0 72#define WTS6 0 73/* WE negate to CSn negate delay for SRAM (0-7:0,1,2,3,4,5,6,7) */ 74#define WTH5 0 75#define WTH6 0 76/* BS hold (0-1:1,2) */ 77#define BSH5 0 78#define BSH6 0 79/* wait cycle (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */ 80#define IW5 6 /* 60ns PIO mode 4 */ 81#define IW6 15 /* 250ns */ 82 83#define SAA5 PCMCIA_IODYN /* IDE area b4000000-b5ffffff */ 84#define SAB5 PCMCIA_IODYN /* CF area b6000000-b7ffffff */ 85#define PCWA5 0 /* additional wait A (0-3:0,15,30,50) */ 86#define PCWB5 0 /* additional wait B (0-3:0,15,30,50) */ 87/* wait B (0-15:0,1,2,3,4,5,6,7,8,9,11,13,15,17,21,25) */ 88#define PCIW5 12 89/* Address->OE/WE assert delay A (0-7:0,1,2,3,6,9,12,15) */ 90#define TEDA5 2 91/* Address->OE/WE assert delay B (0-7:0,1,2,3,6,9,12,15) */ 92#define TEDB5 4 93/* OE/WE negate->Address delay A (0-7:0,1,2,3,6,9,12,15) */ 94#define TEHA5 2 95/* OE/WE negate->Address delay B (0-7:0,1,2,3,6,9,12,15) */ 96#define TEHB5 3 97 98#define CS5BCR_D ((IWW5<<28)|(IWRWD5<<24)|(IWRWS5<<20)| \ 99 (IWRRD5<<16)|(IWRRS5<<12)|(BST5<<10)| \ 100 (SZ5<<8)|(RDSPL5<<7)|(BW5<<4)|(MPX5<<3)|TYPE5) 101#define CS5WCR_D ((ADS5<<28)|(ADH5<<24)|(RDS5<<20)| \ 102 (RDH5<<16)|(WTS5<<12)|(WTH5<<8)|(BSH5<<4)|IW5) 103#define CS5PCR_D ((SAA5<<28)|(SAB5<<24)|(PCWA5<<22)| \ 104 (PCWB5<<20)|(PCIW5<<16)|(TEDA5<<12)| \ 105 (TEDB5<<8)|(TEHA5<<4)|TEHB5) 106 107#define SMC0_BASE 0xb0800000 /* eth0 */ 108#define SMC1_BASE 0xb0900000 /* eth1 */ 109#define CF_BASE 0xb6100000 /* Compact Flash (I/O area) */ 110#define IDE_BASE 0xb4000000 /* IDE */ 111#define PC104_IO_BASE 0xb8000000 112#define PC104_MEM_BASE 0xba000000 113#define SMC_IO_SIZE 0x100 114 115#define CF_OFFSET 0x1f0 116#define IDE_OFFSET 0x170 117 118#endif /* __MACH_SH2007_H */