cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

mrshpc.h (1547B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2#ifndef __MACH_SE_MRSHPC_H
      3#define __MACH_SE_MRSHPC_H
      4
      5#include <linux/io.h>
      6
      7static inline void __init mrshpc_setup_windows(void)
      8{
      9	if ((__raw_readw(MRSHPC_CSR) & 0x000c) != 0)
     10		return;	/* Not detected */
     11
     12	if ((__raw_readw(MRSHPC_CSR) & 0x0080) == 0) {
     13		__raw_writew(0x0674, MRSHPC_CPWCR); /* Card Vcc is 3.3v? */
     14	} else {
     15		__raw_writew(0x0678, MRSHPC_CPWCR); /* Card Vcc is 5V */
     16	}
     17
     18	/*
     19	 *  PC-Card window open
     20	 *  flag == COMMON/ATTRIBUTE/IO
     21	 */
     22	/* common window open */
     23	__raw_writew(0x8a84, MRSHPC_MW0CR1);
     24	if((__raw_readw(MRSHPC_CSR) & 0x4000) != 0)
     25		/* common mode & bus width 16bit SWAP = 1*/
     26		__raw_writew(0x0b00, MRSHPC_MW0CR2);
     27	else
     28		/* common mode & bus width 16bit SWAP = 0*/
     29		__raw_writew(0x0300, MRSHPC_MW0CR2);
     30
     31	/* attribute window open */
     32	__raw_writew(0x8a85, MRSHPC_MW1CR1);
     33	if ((__raw_readw(MRSHPC_CSR) & 0x4000) != 0)
     34		/* attribute mode & bus width 16bit SWAP = 1*/
     35		__raw_writew(0x0a00, MRSHPC_MW1CR2);
     36	else
     37		/* attribute mode & bus width 16bit SWAP = 0*/
     38		__raw_writew(0x0200, MRSHPC_MW1CR2);
     39
     40	/* I/O window open */
     41	__raw_writew(0x8a86, MRSHPC_IOWCR1);
     42	__raw_writew(0x0008, MRSHPC_CDCR);	 /* I/O card mode */
     43	if ((__raw_readw(MRSHPC_CSR) & 0x4000) != 0)
     44		__raw_writew(0x0a00, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1*/
     45	else
     46		__raw_writew(0x0200, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0*/
     47
     48	__raw_writew(0x2000, MRSHPC_ICR);
     49	__raw_writeb(0x00, PA_MRSHPC_MW2 + 0x206);
     50	__raw_writeb(0x42, PA_MRSHPC_MW2 + 0x200);
     51}
     52
     53#endif /* __MACH_SE_MRSHPC_H */