cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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probe.c (1844B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * arch/sh/kernel/cpu/sh2/probe.c
      4 *
      5 * CPU Subtype Probing for SH-2.
      6 *
      7 * Copyright (C) 2002 Paul Mundt
      8 */
      9#include <linux/init.h>
     10#include <linux/of_fdt.h>
     11#include <linux/smp.h>
     12#include <linux/io.h>
     13#include <asm/processor.h>
     14#include <asm/cache.h>
     15
     16#if defined(CONFIG_CPU_J2)
     17extern u32 __iomem *j2_ccr_base;
     18static int __init scan_cache(unsigned long node, const char *uname,
     19			     int depth, void *data)
     20{
     21	if (!of_flat_dt_is_compatible(node, "jcore,cache"))
     22		return 0;
     23
     24	j2_ccr_base = (u32 __iomem *)of_flat_dt_translate_address(node);
     25
     26	return 1;
     27}
     28#endif
     29
     30void __ref cpu_probe(void)
     31{
     32#if defined(CONFIG_CPU_SUBTYPE_SH7619)
     33	boot_cpu_data.type			= CPU_SH7619;
     34	boot_cpu_data.dcache.ways		= 4;
     35	boot_cpu_data.dcache.way_incr	= (1<<12);
     36	boot_cpu_data.dcache.sets		= 256;
     37	boot_cpu_data.dcache.entry_shift	= 4;
     38	boot_cpu_data.dcache.linesz		= L1_CACHE_BYTES;
     39	boot_cpu_data.dcache.flags		= 0;
     40#endif
     41
     42#if defined(CONFIG_CPU_J2)
     43#if defined(CONFIG_SMP)
     44	unsigned cpu = hard_smp_processor_id();
     45#else
     46	unsigned cpu = 0;
     47#endif
     48	if (cpu == 0) of_scan_flat_dt(scan_cache, NULL);
     49	if (j2_ccr_base) __raw_writel(0x80000303, j2_ccr_base + 4*cpu);
     50	if (cpu != 0) return;
     51	boot_cpu_data.type			= CPU_J2;
     52
     53	/* These defaults are appropriate for the original/current
     54	 * J2 cache. Once there is a proper framework for getting cache
     55	 * info from device tree, we should switch to that. */
     56	boot_cpu_data.dcache.ways		= 1;
     57	boot_cpu_data.dcache.sets		= 256;
     58	boot_cpu_data.dcache.entry_shift	= 5;
     59	boot_cpu_data.dcache.linesz		= 32;
     60	boot_cpu_data.dcache.flags		= 0;
     61
     62	boot_cpu_data.flags |= CPU_HAS_CAS_L;
     63#else
     64	/*
     65	 * SH-2 doesn't have separate caches
     66	 */
     67	boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
     68#endif
     69	boot_cpu_data.icache = boot_cpu_data.dcache;
     70	boot_cpu_data.family = CPU_FAMILY_SH2;
     71}