cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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clock-sh7706.c (1945B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * arch/sh/kernel/cpu/sh3/clock-sh7706.c
      4 *
      5 * SH7706 support for the clock framework
      6 *
      7 *  Copyright (C) 2006  Takashi YOSHII
      8 *
      9 * Based on arch/sh/kernel/cpu/sh3/clock-sh7709.c
     10 *  Copyright (C) 2005  Andriy Skulysh
     11 */
     12#include <linux/init.h>
     13#include <linux/kernel.h>
     14#include <asm/clock.h>
     15#include <asm/freq.h>
     16#include <asm/io.h>
     17
     18static int stc_multipliers[] = { 1, 2, 4, 1, 3, 6, 1, 1 };
     19static int ifc_divisors[]    = { 1, 2, 4, 1, 3, 1, 1, 1 };
     20static int pfc_divisors[]    = { 1, 2, 4, 1, 3, 6, 1, 1 };
     21
     22static void master_clk_init(struct clk *clk)
     23{
     24	int frqcr = __raw_readw(FRQCR);
     25	int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
     26
     27	clk->rate *= pfc_divisors[idx];
     28}
     29
     30static struct sh_clk_ops sh7706_master_clk_ops = {
     31	.init		= master_clk_init,
     32};
     33
     34static unsigned long module_clk_recalc(struct clk *clk)
     35{
     36	int frqcr = __raw_readw(FRQCR);
     37	int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
     38
     39	return clk->parent->rate / pfc_divisors[idx];
     40}
     41
     42static struct sh_clk_ops sh7706_module_clk_ops = {
     43	.recalc		= module_clk_recalc,
     44};
     45
     46static unsigned long bus_clk_recalc(struct clk *clk)
     47{
     48	int frqcr = __raw_readw(FRQCR);
     49	int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
     50
     51	return clk->parent->rate / stc_multipliers[idx];
     52}
     53
     54static struct sh_clk_ops sh7706_bus_clk_ops = {
     55	.recalc		= bus_clk_recalc,
     56};
     57
     58static unsigned long cpu_clk_recalc(struct clk *clk)
     59{
     60	int frqcr = __raw_readw(FRQCR);
     61	int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
     62
     63	return clk->parent->rate / ifc_divisors[idx];
     64}
     65
     66static struct sh_clk_ops sh7706_cpu_clk_ops = {
     67	.recalc		= cpu_clk_recalc,
     68};
     69
     70static struct sh_clk_ops *sh7706_clk_ops[] = {
     71	&sh7706_master_clk_ops,
     72	&sh7706_module_clk_ops,
     73	&sh7706_bus_clk_ops,
     74	&sh7706_cpu_clk_ops,
     75};
     76
     77void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
     78{
     79	if (idx < ARRAY_SIZE(sh7706_clk_ops))
     80		*ops = sh7706_clk_ops[idx];
     81}