cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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serial-sh7720.c (1119B)

      1// SPDX-License-Identifier: GPL-2.0
      2#include <linux/serial_sci.h>
      3#include <linux/serial_core.h>
      4#include <linux/io.h>
      5#include <cpu/serial.h>
      6#include <cpu/gpio.h>
      7
      8static void sh7720_sci_init_pins(struct uart_port *port, unsigned int cflag)
      9{
     10	unsigned short data;
     11
     12	if (cflag & CRTSCTS) {
     13		/* enable RTS/CTS */
     14		if (port->mapbase == 0xa4430000) { /* SCIF0 */
     15			/* Clear PTCR bit 9-2; enable all scif pins but sck */
     16			data = __raw_readw(PORT_PTCR);
     17			__raw_writew((data & 0xfc03), PORT_PTCR);
     18		} else if (port->mapbase == 0xa4438000) { /* SCIF1 */
     19			/* Clear PVCR bit 9-2 */
     20			data = __raw_readw(PORT_PVCR);
     21			__raw_writew((data & 0xfc03), PORT_PVCR);
     22		}
     23	} else {
     24		if (port->mapbase == 0xa4430000) { /* SCIF0 */
     25			/* Clear PTCR bit 5-2; enable only tx and rx  */
     26			data = __raw_readw(PORT_PTCR);
     27			__raw_writew((data & 0xffc3), PORT_PTCR);
     28		} else if (port->mapbase == 0xa4438000) { /* SCIF1 */
     29			/* Clear PVCR bit 5-2 */
     30			data = __raw_readw(PORT_PVCR);
     31			__raw_writew((data & 0xffc3), PORT_PVCR);
     32		}
     33	}
     34}
     35
     36struct plat_sci_port_ops sh7720_sci_port_ops = {
     37	.init_pins	= sh7720_sci_init_pins,
     38};