clock-sh7722.c (7592B)
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * arch/sh/kernel/cpu/sh4a/clock-sh7722.c 4 * 5 * SH7722 clock framework support 6 * 7 * Copyright (C) 2009 Magnus Damm 8 */ 9#include <linux/init.h> 10#include <linux/kernel.h> 11#include <linux/io.h> 12#include <linux/clkdev.h> 13#include <linux/sh_clk.h> 14#include <asm/clock.h> 15#include <cpu/sh7722.h> 16 17/* SH7722 registers */ 18#define FRQCR 0xa4150000 19#define VCLKCR 0xa4150004 20#define SCLKACR 0xa4150008 21#define SCLKBCR 0xa415000c 22#define IRDACLKCR 0xa4150018 23#define PLLCR 0xa4150024 24#define MSTPCR0 0xa4150030 25#define MSTPCR1 0xa4150034 26#define MSTPCR2 0xa4150038 27#define DLLFRQ 0xa4150050 28 29/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 30static struct clk r_clk = { 31 .rate = 32768, 32}; 33 34/* 35 * Default rate for the root input clock, reset this with clk_set_rate() 36 * from the platform code. 37 */ 38struct clk extal_clk = { 39 .rate = 33333333, 40}; 41 42/* The dll block multiplies the 32khz r_clk, may be used instead of extal */ 43static unsigned long dll_recalc(struct clk *clk) 44{ 45 unsigned long mult; 46 47 if (__raw_readl(PLLCR) & 0x1000) 48 mult = __raw_readl(DLLFRQ); 49 else 50 mult = 0; 51 52 return clk->parent->rate * mult; 53} 54 55static struct sh_clk_ops dll_clk_ops = { 56 .recalc = dll_recalc, 57}; 58 59static struct clk dll_clk = { 60 .ops = &dll_clk_ops, 61 .parent = &r_clk, 62 .flags = CLK_ENABLE_ON_INIT, 63}; 64 65static unsigned long pll_recalc(struct clk *clk) 66{ 67 unsigned long mult = 1; 68 unsigned long div = 1; 69 70 if (__raw_readl(PLLCR) & 0x4000) 71 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1); 72 else 73 div = 2; 74 75 return (clk->parent->rate * mult) / div; 76} 77 78static struct sh_clk_ops pll_clk_ops = { 79 .recalc = pll_recalc, 80}; 81 82static struct clk pll_clk = { 83 .ops = &pll_clk_ops, 84 .flags = CLK_ENABLE_ON_INIT, 85}; 86 87struct clk *main_clks[] = { 88 &r_clk, 89 &extal_clk, 90 &dll_clk, 91 &pll_clk, 92}; 93 94static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; 95static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 }; 96 97static struct clk_div_mult_table div4_div_mult_table = { 98 .divisors = divisors, 99 .nr_divisors = ARRAY_SIZE(divisors), 100 .multipliers = multipliers, 101 .nr_multipliers = ARRAY_SIZE(multipliers), 102}; 103 104static struct clk_div4_table div4_table = { 105 .div_mult_table = &div4_div_mult_table, 106}; 107 108#define DIV4(_reg, _bit, _mask, _flags) \ 109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 110 111enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; 112 113struct clk div4_clks[DIV4_NR] = { 114 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), 115 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), 116 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), 117 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), 118 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), 119 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0), 120}; 121 122enum { DIV4_IRDA, DIV4_ENABLE_NR }; 123 124struct clk div4_enable_clks[DIV4_ENABLE_NR] = { 125 [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0), 126}; 127 128enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR }; 129 130struct clk div4_reparent_clks[DIV4_REPARENT_NR] = { 131 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0), 132 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0), 133}; 134 135enum { DIV6_V, DIV6_NR }; 136 137struct clk div6_clks[DIV6_NR] = { 138 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), 139}; 140 141static struct clk mstp_clks[HWBLK_NR] = { 142 [HWBLK_URAM] = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 143 [HWBLK_XYMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 144 [HWBLK_TMU] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), 145 [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0), 146 [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0), 147 [HWBLK_FLCTL] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), 148 [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0), 149 [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 6, 0), 150 [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0), 151 152 [HWBLK_IIC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0), 153 [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 8, 0), 154 155 [HWBLK_SDHI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 18, 0), 156 [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR2, 14, 0), 157 [HWBLK_USBF] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 11, 0), 158 [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0), 159 [HWBLK_SIU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 8, 0), 160 [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0), 161 [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0), 162 [HWBLK_BEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0), 163 [HWBLK_CEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0), 164 [HWBLK_VEU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0), 165 [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0), 166 [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 0, 0), 167}; 168 169static struct clk_lookup lookups[] = { 170 /* main clocks */ 171 CLKDEV_CON_ID("rclk", &r_clk), 172 CLKDEV_CON_ID("extal", &extal_clk), 173 CLKDEV_CON_ID("dll_clk", &dll_clk), 174 CLKDEV_CON_ID("pll_clk", &pll_clk), 175 176 /* DIV4 clocks */ 177 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), 178 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]), 179 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), 180 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), 181 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]), 182 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), 183 CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]), 184 CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]), 185 CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]), 186 187 /* DIV6 clocks */ 188 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), 189 190 /* MSTP clocks */ 191 CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]), 192 CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]), 193 194 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[HWBLK_TMU]), 195 196 CLKDEV_ICK_ID("fck", "sh-cmt-32.0", &mstp_clks[HWBLK_CMT]), 197 CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]), 198 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]), 199 200 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[HWBLK_SCIF0]), 201 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[HWBLK_SCIF1]), 202 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[HWBLK_SCIF2]), 203 204 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC]), 205 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), 206 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI]), 207 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]), 208 CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]), 209 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), 210 CLKDEV_DEV_ID("siu-pcm-audio", &mstp_clks[HWBLK_SIU]), 211 CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]), 212 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]), 213 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]), 214 CLKDEV_DEV_ID("renesas-ceu.0", &mstp_clks[HWBLK_CEU]), 215 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]), 216 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), 217 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]), 218}; 219 220int __init arch_clk_init(void) 221{ 222 int k, ret = 0; 223 224 /* autodetect extal or dll configuration */ 225 if (__raw_readl(PLLCR) & 0x1000) 226 pll_clk.parent = &dll_clk; 227 else 228 pll_clk.parent = &extal_clk; 229 230 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 231 ret = clk_register(main_clks[k]); 232 233 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 234 235 if (!ret) 236 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 237 238 if (!ret) 239 ret = sh_clk_div4_enable_register(div4_enable_clks, 240 DIV4_ENABLE_NR, &div4_table); 241 242 if (!ret) 243 ret = sh_clk_div4_reparent_register(div4_reparent_clks, 244 DIV4_REPARENT_NR, &div4_table); 245 246 if (!ret) 247 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 248 249 if (!ret) 250 ret = sh_clk_mstp_register(mstp_clks, HWBLK_NR); 251 252 return ret; 253}