cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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udivsi3.S (1015B)


      1/* SPDX-License-Identifier: GPL-2.0+ WITH GCC-exception-2.0
      2
      3   Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
      4   2004, 2005
      5   Free Software Foundation, Inc.
      6*/
      7
      8!! libgcc routines for the Renesas / SuperH SH CPUs.
      9!! Contributed by Steve Chamberlain.
     10!! sac@cygnus.com
     11
     12	.balign 4
     13	.global	__udivsi3
     14	.type	__udivsi3, @function
     15div8:
     16	div1 r5,r4
     17div7:
     18	div1 r5,r4; div1 r5,r4; div1 r5,r4
     19	div1 r5,r4; div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
     20
     21divx4:
     22	div1 r5,r4; rotcl r0
     23	div1 r5,r4; rotcl r0
     24	div1 r5,r4; rotcl r0
     25	rts; div1 r5,r4
     26
     27__udivsi3:
     28	sts.l pr,@-r15
     29	extu.w r5,r0
     30	cmp/eq r5,r0
     31	bf/s large_divisor
     32	div0u
     33	swap.w r4,r0
     34	shlr16 r4
     35	bsr div8
     36	shll16 r5
     37	bsr div7
     38	div1 r5,r4
     39	xtrct r4,r0
     40	xtrct r0,r4
     41	bsr div8
     42	swap.w r4,r4
     43	bsr div7
     44	div1 r5,r4
     45	lds.l @r15+,pr
     46	xtrct r4,r0
     47	swap.w r0,r0
     48	rotcl r0
     49	rts
     50	shlr16 r5
     51
     52large_divisor:
     53	mov #0,r0
     54	xtrct r4,r0
     55	xtrct r0,r4
     56	bsr divx4
     57	rotcl r0
     58	bsr divx4
     59	rotcl r0
     60	bsr divx4
     61	rotcl r0
     62	bsr divx4
     63	rotcl r0
     64	lds.l @r15+,pr
     65	rts
     66	rotcl r0