cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pil.h (1109B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2#ifndef _SPARC64_PIL_H
      3#define _SPARC64_PIL_H
      4
      5/* To avoid some locking problems, we hard allocate certain PILs
      6 * for SMP cross call messages that must do a etrap/rtrap.
      7 *
      8 * A local_irq_disable() does not block the cross call delivery, so
      9 * when SMP locking is an issue we reschedule the event into a PIL
     10 * interrupt which is blocked by local_irq_disable().
     11 *
     12 * In fact any XCALL which has to etrap/rtrap has a problem because
     13 * it is difficult to prevent rtrap from running BH's, and that would
     14 * need to be done if the XCALL arrived while %pil==PIL_NORMAL_MAX.
     15 *
     16 * Finally, in order to handle profiling events even when a
     17 * local_irq_disable() is in progress, we only disable up to level 14
     18 * interrupts.  Profile counter overflow interrupts arrive at level
     19 * 15.
     20 */
     21#define PIL_SMP_CALL_FUNC	1
     22#define PIL_SMP_RECEIVE_SIGNAL	2
     23#define PIL_SMP_CAPTURE		3
     24#define PIL_DEVICE_IRQ		5
     25#define PIL_SMP_CALL_FUNC_SNGL	6
     26#define PIL_DEFERRED_PCR_WORK	7
     27#define PIL_KGDB_CAPTURE	8
     28#define PIL_NORMAL_MAX		14
     29#define PIL_NMI			15
     30
     31#endif /* !(_SPARC64_PIL_H) */